Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2001-10-03
2003-11-25
Gaffin, Jeffrey (Department: 2183)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S052000, C710S061000, C713S400000
Reexamination Certificate
active
06654824
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates generally to the transfer of data in data processing systems and more particularly to the transfer of data across multi-lane communications links wherein the transmission times of the respective lanes may be different.
2. Background of the Invention
Referring to
FIG. 1
, a point-to-point communications link consists of three basic elements: a transmitter
10
; a communications medium
12
; and a receiver
14
. Generally speaking, transmitter
10
transmits data using a local clock signal. Receiver
14
likewise uses a local clock signal to receive the data, but this clock signal is local to the receiver, and not the transmitter. Put another way, the clock signal's used by transmitter
10
and receiver
14
are generated from different sources and are not identical. Transmitter
10
and receiver
14
can therefore be said to reside in different clock domains. (Each clock domain comprises the portion of the system in which the respective clock signal is used as the basis for transferring data or perform its respective operations.)
While the clock signals in each clock domain may be designed to have the same frequency, it is virtually impossible to generate identical clock signals in any two clock domains. Typically, there is a phase mismatch and a slight frequency mismatch between the clock signals. The phase difference between the two signals can easily be handled by inserting a buffer (sometimes referred to as an elastic buffer) in the communications link so that data is written to the buffer according to the clock signal of the transmitting domain and retrieved from the buffer according to clock signal of the receiving domain. The frequency mismatch may cause the amount of data in each buffer to gradually increase or decrease, potentially causing an overflow or underflow condition. If the data in the buffer were allowed to overflow or underflow, the data stream delivered by the communications link would be corrupted. The problem of buffer overflow/underflow in a single communications channel can be resolved through the use of fill words which are added to or deleted from an elastic buffer. Fill words are a set of predefined symbols which occupy positions in the data stream, but which do not carry any of the information being transferred. As the amount of data in the elastic buffer approaches an overflow condition, fill words can be deleted from the output data stream. This effectively allows the output to catch up with the input. As the amount of data in the elastic buffer approaches an underflow condition, fill words can be added to the output data stream. This effectively allows slows down the output so that the input can catch up with it.
This single-channel solution to the problem of buffer overflow/underflow cannot, however, be directly implemented in a multilane communications link. If each lane of the communications link were allowed to add or delete fill words as appropriate to relieve overflow or underflow conditions in that lane, the data stream in that lane would be skewed with respect to the data streams in the other lanes. Then, when the separate data streams were de-multiplexed into a single data stream at the receiving end of the communications link, the data symbols within the reconstructed data stream would be out of order, and the data stream would be corrupted. Another problem which arises in multi-lane communications links is that, even absent the effects of adding or deleting fill words, the data streams in the different lanes may be skewed with respect to each other. This skewing may be caused, in part, by phase differences in the clock signals which are used to transmit data in the different lanes. Even more pronounced skewing may be caused by differences in the transmission lengths of the different lanes. (Transmission length is used here to refer to the amount of time it takes for a piece of data to be transmitted over the length of the corresponding transmission lane.) As indicated above, the skewing of the data streams may result in corruption of the data at the receiving end of the communications link.
SUMMARY OF INVENTION
One or more of the problems outlined above may be solved by the various embodiments of the invention. Broadly speaking, the invention comprises systems and methods for enabling data transfers over multi-lane communications links, wherein each of the lanes may have a different transmission length. After a reset event, a test sequence comprising a plurality of test sequence symbols is transmitted over the communications link, with at least one of the test sequence symbols being transmitted over each of the transmission lanes. The data transmitted via each lane is examined at the receiving end of the communications link. The data received via a particular transmission lane is stored in a corresponding buffer only after a test sequence symbol is received from that lane. Once a test sequence symbol is received via each of the transmission lanes, data can begin to be read out of the buffers corresponding to each of the lanes. If the amount of data accumulated in any one of the buffers exceeds a predetermined maximum, all of the buffers are reset and a new test sequence must be transmitted over the communications link.
In one embodiment, a system comprises a plurality of buffers, each of which is coupled to one of a plurality of transmission lanes in a communications link. Each of the buffers is configured to reset corresponding read and write pointers to predetermined initial positions upon the occurrence of a reset event. Each buffer is configured to maintain these pointer positions until a test sequence symbol is received. After the test sequence symbol is detected, the write pointer is advanced by one storage location for each data symbol, so that the data symbols are consecutively stored in the buffer. Each buffer is also configured to assert an ALIGNED signal after the test sequence symbol is received. The ALIGNED signal from each of the buffers is conveyed to a controller. The controller is configured to assert a DESKEWED signal when the ALIGNED signals for all of the buffers are asserted. The DESKEWED signal is conveyed to each of the buffers and, when this signal is asserted, the reading of data out of each buffer is initiated, with the read pointer of each buffer trailing the corresponding write pointer by an amount which compensates for the corresponding transmission length skew.
In another embodiment, a method comprises providing a plurality of buffers, each of which corresponds to one of the transmission lanes of a multi-lane communications link. After a reset event, the data received via each of the transmission lanes is monitored to identify receipt of a test sequence symbol. After the test sequence symbol has been received via a particular transmission lane, subsequent data received via that lane is stored in the corresponding buffer. After test sequence symbols have been received via all of the transmission lanes in the communications link, data begins to be read out of each of the buffers. The data symbols are then reconstructed into a single data stream.
REFERENCES:
patent: 6321252 (2001-11-01), Bhola et al.
Mateus Marcus Sebastian
Umberhocker Richard B.
Vila Diego Fernando
Crossroads Systems Inc.
Gaffin Jeffrey
Gray Cary Ware & Freidenrich LLP
Knapp Justin
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