Input/output cell with a programmable delay element

Details Input/output cell with a programmable delay element Input/output cell with a programmable delay element

2001-01-19

2004-03-16

Heckler, Thomas (Department: 2185)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C713S401000

Reexamination Certificate

active

06708238

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to system bus input/output cells for computer systems, and more particularly to an input/output cell with a programmable delay element therein.
BACKGROUND OF THE INVENTION
A system bus is an electronic highway in a digital computer that provides a communication path for data to flow between the central processing unit (CPU) and it's memory unit and between and among the CPU and the various peripheral devices connected to the computer's input/output unit. A system bus contains one wire for each bit needed to specify the address of a device or location in memory, plus additional wires that distinguish among the various data transfer operations to be performed. A system bus can transmit data in either direction between any two components of the computing system through the use of input/output (IO) cells.
IO cells are semiconductor circuit devices generally embedded in a semiconductor material core, which are designed to send (output cells) or receive (input cells) binary data signals throughout the system bus. The IO cell may include a single output cell, a single input cell or any combination of both. By way of examples, IO cells may be used in a system bus for a computer system, or in the various internal busses and system bus interface units within a CPU, or may be stand alone devices on an integrated circuit chip.
To meet the high frequency cycle times of system busses, output cells are designed to be fast. However, this may cause the receiver cells to incorrectly capture the binary signals if the timing requirements for setting up and holding the binary signals are not properly matched between the receiver cells and the output cells. Complicating this is the fact that IO cell can be used across many different platforms, e.g., single processor work stations, single processor servers or multiple processor servers, which can vary in their output time requirements.
Moreover, the input and output response times of these IO cells will vary within different tolerance ranges as ambient conditions change. Generally the fastest response times occur under cold temperatures and high voltage conditions, while the slowest response times occur under hot temperatures and low voltage conditions.
Additionally, the transmission times will vary with the length of the metal traces and the number of logic elements that the signal must propagate through between output cell and receiver cell. In large systems, where the output and receiver cells are generally far apart, the transmission times will be longer because the signal must travel through much longer run lengths. In small systems the transmission times are relatively smaller, because of the shorter runs. When the output cells and input cells are located on a single printed circuit board, the transmission time therebetween is called the board trace delay.
With a single IO cell, having a fixed range of response time, it is very difficult to meet the wide range of minimum/maximum output and input time requirements it may encounter. Prior art IO cells have had to redesign new silicon runs or traces into the IO cells themselves to meet varying conditions. This process can be expensive and time consuming.
Another problem occurs when an Application Specific Integrated Circuit (ASIC) process is used to custom design a system to meet specific customer requirements. It is often difficult to determine the range of variability in the ASIC process required of the IO cell used in the design of the custom system. In order to do so, test boards must be designed with delay elements incorporated onto the test board itself in order to empirically determine the proper delay times to match the output cell timing requirements to the input cell timing requirements. This can increase the time and cost of testing in an ASIC process design.
Accordingly, there is a need for an improved IO cell for the transmission of binary signals.
SUMMARY OF THE INVENTION
The present invention offers advantages and alternatives over the prior art by providing an IO cell with a programmable delay element therein. The delay element enables the tuning of an output IO cell's timing requirements to an input IO cell's timing requirements to provide a transmission path therebetween. Advantageously, the timing requirements of the IO cells may be met in systems with both long and short board trace delays and under various environments conditions. Additionally, the timing requirements of the IO cells in a transmission path can be met without having to redesign new silicon runs or traces into the IO cells.
These and other advantages are accomplished in an exemplary embodiment of the invention by providing an IO cell for providing a transmission path for a binary signal. The IO cell includes an IO buffer for amplifying the binary signal. A programmable delay element is electrically connected to the IO buffer such that the binary signal transmits from the programmable delay element to the IO buffer. The delay element is responsive to “n” number of programmable binary bits to selectively delay transmission of the binary signal by a set of predetermined delay time ranges. An IO pad is connected in series with the IO buffer and the programmable delay element.
In an alternative embodiment of the invention, the IO cell includes an output cell for transmitting the binary signal. The output cell has the IO pad electrically connected to the IO buffer such that the binary signal transmits from the IO buffer to the IO pad.
In another alternative embodiment of the invention, the IO cell includes an input cell for receiving the binary signal. The input cell has the IO pad electrically connected to the programmable delay element such that the binary signal transmits from the IO pad to the programmable delay element.
In another alternative embodiment of the invention, the delay element of the IO cell includes a multiplexer having an output electrically connected to an input of the IO buffer. The multiplexer also has “n” number of selection inputs for receiving the “n” number of the programmable bits and set of mux inputs electrically connected to the binary signal. Each mux input is selectable by the programmable bits to delay transmission of the binary signal by one of the delay time ranges.


REFERENCES:
patent: 6256681 (2001-07-01), Chang
patent: 6453443 (2002-09-01), Chen et al.
patent: 6487682 (2002-11-01), Yamamura et al.
patent: 6560760 (2003-05-01), Nagai

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