Low latency FIFO circuit for mixed clock systems
Low latency queue pairs for I/O adapters
Low latency send queues in I/O adapter hardware
Maintaining remote queue using two counters in transfer...
Managed file system filter model and architecture
Management of display FIFO requests for DRAM access wherein low
Managing a buffer for media processing
Managing bus transaction dependencies
Managing bus transaction dependencies
Managing data flows in a parallel processing environment
Managing multiple host requests in queued commands that...
Managing queue capacity in a messaging queue in a computing...
Mechanism to control the allocation of an N-source shared...
Memory configuration with I/O support
Memory control apparatus and memory control method
Memory controller having a buffer for providing beginning...
Memory controller with automatic command processing unit and...
Memory handling system that backfills dual-port buffer from over
Memory interface circuit and method
Memory interface controller for a network device