Management of display FIFO requests for DRAM access wherein low

Details Management of display FIFO requests for DRAM access wherein low Management of display FIFO requests for DRAM access wherein low

1998-07-17

2000-11-07

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 52, 710 53, 710 60, 711151, 711158, G06F 1314

Patent

active

061450332

ABSTRACT:
A display FIFO module is used in a DRAM interface. A low priority request and high priority request are both issued when the FIFO must receive new data or FIFO underrun will occur. This is determined by comparing the FIFO data level against a predetermined high threshold value. After a predetermined number of addresses have been latched by a DRAM controller sequencer to the DRAM for transferring data to the FIFO because of either the low or high priority request, or both, the display FIFO module reevaluates the FIFO data level to determine whether the FIFO data level is still below or is equal to either the low or high threshold value. If the FIFO data level is still below or equal to the low threshold value, the low priority request remains active; otherwise, the low priority request will be removed by the display FIFO module. Similarly, if the FIFO data level is still below or equal to the high threshold value, the high priority request remains active; otherwise, the high priority request will be removed by the display FIFO module.

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Mar. 18, 1997 Written Opinion under PCT Rule 66 from IPEA/EPO PCT/US96/07373.

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