Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2005-05-10
2005-05-10
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S057000, C710S033000, C710S034000
Reexamination Certificate
active
06892253
ABSTRACT:
The data transfer apparatus and method employs two queue counters to maintain the status of a first-in-first-out buffer memory. A master count (251) indicates the number of entries available for use within the FIFO (410). New data can be allocated to the FIFO only if this master count is non-zero. This master count is decremented (401) upon allocation of new data to the FIFO. A remote count (252) stores the number of data entries stored in the FIFO. This remote count is incremented (413) upon allocation of data to the FIFO and decremented (414) upon reading data from the FIFO. A confirm decrement signal (408) from the remote count triggers an increment of the master count. This two counter technique makes better use of the available bandwidth than the prior art by not requiring a FIFO depth equal the to the data transfer latency. This technique is particularly useful in systems with delays between the data source and data destination and a mismatch of maximum data transfer rates.
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Brady III W. James
Gaffin Jeffrey
Marshall, Jr. Robert D.
Martinez David
Telecky , Jr. Frederick J.
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