Managing bus transaction dependencies

Details Managing bus transaction dependencies Managing bus transaction dependencies

2006-07-25

2006-07-25

Vo, Tim (Department: 2112)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S056000

Reexamination Certificate

active

07082480

ABSTRACT:
A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

REFERENCES:
patent: 5006982 (1991-04-01), Ebersole et al.
patent: 5467295 (1995-11-01), Young et al.
patent: 5887194 (1999-03-01), Carson et al.
patent: 5930485 (1999-07-01), Kelly
patent: 6145032 (2000-11-01), Bannister et al.

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