Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2007-05-01
2007-05-01
Flynn, Nathan J. (Department: 2154)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S053000, C709S232000, C370S229000
Reexamination Certificate
active
09651924
ABSTRACT:
A method and apparatus for ensuring fair and efficient use of a shared memory buffer. A preferred embodiment comprises a shared memory buffer in a multi-processor computer system. Memory requests from a local processor are delivered to a local memory controller by a cache control unit and memory requests from other processors are delivered to the memory controller by an interprocessor router. The memory controller allocates the memory requests in a shared buffer using a credit-based allocation scheme. The cache control unit and the interprocessor router are each assigned a number of credits. Each must pay a credit to the memory controller when a request is allocated to the shared buffer. If the number of filled spaces in the shared buffer is below a threshold, the buffer immediately returns the credits to the source from which the credit and memory request arrived. If the number of filled spaces in the shared buffer is above a threshold, the buffer holds the credits and returns the credits in a round-robin manner only when a space in the shared buffer becomes free. The number of credits assigned to each source is sufficient to enable each source to deliver an uninterrupted burst of memory requests to the buffer without having to wait for credits to return from the buffer. The threshold is the point when the number of free spaces available in the buffer is equal to the total number of credits assigned to the cache control unit and the interprocessor router.
REFERENCES:
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5317718 (1994-05-01), Jouppi
patent: 5446734 (1995-08-01), Goldstein
patent: 5758183 (1998-05-01), Scales
patent: 5761729 (1998-06-01), Scales
patent: 5787480 (1998-07-01), Scales et al.
patent: 5802585 (1998-09-01), Scales et al.
patent: 5809450 (1998-09-01), Chrysos et al.
patent: 5875151 (1999-02-01), Mick
patent: 5890201 (1999-03-01), McLellan et al.
patent: 5893931 (1999-04-01), Peng et al.
patent: 5898671 (1999-04-01), Hunt et al.
patent: 5918250 (1999-06-01), Hammond
patent: 5918251 (1999-06-01), Yamada et al.
patent: 5923872 (1999-07-01), Chrysos et al.
patent: 5950228 (1999-09-01), Scales et al.
patent: 5958019 (1999-09-01), Hagersten et al.
patent: 5964867 (1999-10-01), Anderson et al.
patent: 5982771 (1999-11-01), Caldara et al.
patent: 5983325 (1999-11-01), Lewchuk
patent: 5999518 (1999-12-01), Nattkemper et al.
patent: 6000044 (1999-12-01), Chrysos et al.
patent: 6044406 (2000-03-01), Barkey et al.
patent: 6070227 (2000-05-01), Rokicki
patent: 6078565 (2000-06-01), Ben-Michael et al.
patent: 6085300 (2000-07-01), Sunaga et al.
patent: 6104727 (2000-08-01), Moura et al.
patent: 6115748 (2000-09-01), Hauser et al.
patent: 6256674 (2001-07-01), Manning et al.
patent: 6347337 (2002-02-01), Shah et al.
patent: 6359884 (2002-03-01), Vincent
patent: 6426957 (2002-07-01), Hauser et al.
patent: 6452903 (2002-09-01), Peck et al.
patent: 6493776 (2002-12-01), Courtright et al.
patent: 6515963 (2003-02-01), Bechtolsheim et al.
patent: 6532501 (2003-03-01), McCracken
patent: 6546453 (2003-04-01), Kessler et al.
patent: 6546465 (2003-04-01), Bertone
patent: 6567900 (2003-05-01), Kessler
patent: 6591349 (2003-07-01), Steinman et al.
patent: 6594701 (2003-07-01), Forin
patent: 6601084 (2003-07-01), Bhaskaran et al.
patent: 6622225 (2003-09-01), Kessler et al.
patent: 6633960 (2003-10-01), Kessler et al.
patent: 6636955 (2003-10-01), Kessler et al.
patent: 6646986 (2003-11-01), Beshai
patent: 6654858 (2003-11-01), Asher et al.
patent: 6662265 (2003-12-01), Kessler et al.
patent: 6662319 (2003-12-01), Webb, Jr. et al.
patent: 6668335 (2003-12-01), Breach et al.
patent: 6671822 (2003-12-01), Asher et al.
patent: 6674722 (2004-01-01), Tiainen et al.
patent: 6678840 (2004-01-01), Kessler et al.
patent: 6681295 (2004-01-01), Root et al.
patent: 6704817 (2004-03-01), Steinman et al.
patent: 6715008 (2004-03-01), Shimizu
patent: 6715057 (2004-03-01), Kessler et al.
patent: 6735174 (2004-05-01), Hefty et al.
patent: 6738836 (2004-05-01), Kessler et al.
patent: 6751698 (2004-06-01), Deneroff et al.
patent: 6751721 (2004-06-01), Webb, Jr. et al.
patent: 6754739 (2004-06-01), Kessler et al.
patent: 6779142 (2004-08-01), Bhavsar et al.
patent: 6961781 (2005-11-01), Mukherjee et al.
patent: 6992984 (2006-01-01), Gu
patent: 7099913 (2006-08-01), Bertone et al.
Are Your PLDs Metastable?, Cypress Semiconductor Corporation, Mar. 6, 1997 (19 p.).
End-to-End Fault Containment In Scalable Shared-Memory Multiprocessors, D. Teodosiu, Jul. 2000 (148 p.).
David H. Asher et al., “A High Performance Way Allocation Strategy For A Multi-Way Associative Cache System,” U.S. Appl. No. 09/653,092, Aug. 31, 2000 (39 p.), application now abandoned.
Alpha Architecture Reference Manual, Third Edition, The Alpha Architecture Committee, 1998 (month unknown) Digital Equipment Corporation (21 p.), in particular pp. 3-1 through 3-15.
A Logic Design Structure For LSI Testability, E. B. Eichelberger et al., 1977 (month unknown) IEEE (pp. 462-468).
Direct RDRAM 256/288-Mbit (512Kx16/18x32s), Preliminary Information Document DL0060 Version 1.01, Apr. 2000 (69 p.).
Testability Features of AMD-K6 Microprocessor, R. S. Fetherston et al., Advanced Micro Devices, 1997 (month unknown) (8 P.).
Hardware Fault Containment in Scalable Shared-Memory Multiprocessors, D. Teodosiu et al., Computer Systems Laboratory, Stanford University (12 p.), Jun. 1977.
Cellular Disco: resource management using virtual clusters on shared-memory multiprocessors, K. Govil et al., 1999 (month unknown) ACM 1-58113-140-2/99/0012 (16 p.).
Rambus RIMM Module (with 128/144Mb RDRAMs), Preliminary Information, Document DL0084 Version 1.1, Apr. 2000 (12 p.).
Direct Rambus RIMM Module Specification Version 1.0, Rambus Inc., SL-0006-100 (32 p.), 2000 (month unknown).
Asher David H.
Bertone Michael S.
Kessler Richard E.
Lang Steve
Flynn Nathan J.
Hewlett--Packard Development Company, L.P.
Nguyen Dustin
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