Hardware semaphores for a multi-processor system within a...
Hiding system latencies in a throughput networking system
Hiding system latencies in a throughput networking systems
Hierarchical memory access via pipelining with deferred...
Hierarchical memory access via pipelining with deferred...
Hierarchically expandable fair arbiter
High speed bus system that incorporates uni-directional...
High-speed starvation-free arbiter system, rotating-priority...
Hybrid switching architecture
Image processing system, and semiconductor device and...
Immediate grant bus arbiter for bus system
Independent reset of arbiters and agents to allow for...
Independent reset of arbiters and agents to allow for...
Information processing apparatus
Information processing apparatus and access control method...
Information processing apparatus with output device selection ba
Information processing apparatus, peripheral apparatus...
Information processing system, bus arbiter, and bus...
Information processing system, bus arbiter, and bus...
Integrated circuit memory devices having clock signal...