Hierarchical memory access via pipelining with deferred...

Details Hierarchical memory access via pipelining with deferred... Hierarchical memory access via pipelining with deferred...

2008-04-01

2008-04-01

Lee, Christopher E. (Department: 2111)

Electrical computers and digital data processing systems: input/

Access arbitrating

Hierarchical or multilevel arbitrating

C711S169000, C711S140000, C712S001000

Reexamination Certificate

active

07353310

ABSTRACT:
A circuit arrangement and method utilize a hierarchical pipelined memory-access structure incorporating deferred arbitration logic. A multi-stage pipelined network defines at least one pipeline between a plurality of initiators and a shared resource. The multi-stage pipelined network includes first and second stages, where the first stage is disposed intermediate the second stage and the shared resource. First and second arbitration circuits are coupled respectively to the first and second stages of the multi-stage pipelined network, with each arbitration circuit configured to receive requests for access to the resource from at least one initiator and forward such requests to the shared resource. The second arbitration circuit is configured to forward requests to the shared resource via the first arbitration circuit, and the first arbitration circuit is configured to communicate at least one arbitration signal to the second arbitration circuit for use by the second arbitration circuit in arbitrating between requests received thereby. The incorporation of deferred arbitration logic enables arbitration logic to span levels of hierarchy, thus enabling the logical design of the memory-access structure to be effectively decoupled from the physical design.

REFERENCES:
patent: 5608881 (1997-03-01), Masumura et al.
patent: 5640527 (1997-06-01), Pecone et al.
patent: 6772254 (2004-08-01), Hofmann et al.
patent: 7024506 (2006-04-01), Harrington
patent: 7046661 (2006-05-01), Oki et al.
patent: 2004/0255088 (2004-12-01), Scheuerlein

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