Hardware semaphores for a multi-processor system within a...

Electrical computers and digital data processing systems: input/ – Access arbitrating – Centralized arbitrating

Reexamination Certificate

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Details

C710S107000, C711S163000

Reexamination Certificate

active

06892258

ABSTRACT:
A circuit generally comprising a memory element and a controller. The memory element may define a semaphore allocatable to a resource. The controller may be configured to (i) present a granted status in response to a processor reading a first address while the semaphore has a free status, (ii) set the semaphore to a busy status in response to presenting the granted status, and (iii) present the busy status in response to the processor reading the first address while the semaphore has the busy status.

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