Hiding system latencies in a throughput networking system

Details Hiding system latencies in a throughput networking system Hiding system latencies in a throughput networking system

2011-07-26

2011-07-26

Knoll, Clifford H (Department: 2111)

Electrical computers and digital data processing systems: input/

Access arbitrating

C711S154000

Reexamination Certificate

active

07987306

ABSTRACT:
A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.

REFERENCES:
patent: 5909686 (1999-06-01), Muller et al.
patent: 5920566 (1999-07-01), Hendel et al.
patent: 5923847 (1999-07-01), Hagersten et al.
patent: 5938736 (1999-08-01), Muller et al.
patent: 5940401 (1999-08-01), Frazier, Jr. et al.
patent: 6014380 (2000-01-01), Hendel et al.
patent: 6016310 (2000-01-01), Muller et al.
patent: 6021132 (2000-02-01), Muller et al.
patent: 6049528 (2000-04-01), Hendel et al.
patent: 6081512 (2000-06-01), Muller et al.
patent: 6081522 (2000-06-01), Hendel et al.
patent: 6088356 (2000-07-01), Hendel et al.
patent: 6115378 (2000-09-01), Hendel et al.
patent: 6128666 (2000-10-01), Muller et al.
patent: 6246680 (2001-06-01), Muller et al.
patent: 6587866 (2003-07-01), Modi et al.
patent: 6591303 (2003-07-01), Hendel et al.
patent: 6633946 (2003-10-01), Hendel
patent: 6667980 (2003-12-01), Modi et al.
patent: 6735206 (2004-05-01), Oki et al.
patent: 7047372 (2006-05-01), Zeitler et al.
patent: 7099986 (2006-08-01), Pettey et al.
patent: 7152128 (2006-12-01), Wehage et al.
patent: 2002/0141256 (2002-10-01), Barri et al.
patent: 2004/0098496 (2004-05-01), Wolrich et al.
patent: 00/36509 (2000-06-01), None
patent: 02/061593 (2002-08-01), None
Marr, Deborah T. et al. “Hyper-Threading Technology Architecture and Microarchitecture”Intel Technology Journalvol. 6, Issue 1, Feb. 14, 2002: pp. 4-57.
Magro, William. et al. “Hyper-Threading Technology: Impact on Compute-Intensive Workloads”Intel Technology Journalvol. 6, Issue 1, Feb. 14, 2002: pp. 58-66.
Melvin, Steve et al. “A Massively Multithreaded Packet Processor”NP2: Workshop on Network Processors, The 9th International Symposium on High-Performance Computer Architecture,Anaheim, California, Feb. 8-9, 2003.
Stevens, W. Richard. TCP/IP Illustrated vol. 1, Chapters 1 and 2: pp. 1-32, Addison-Wesley, 1996.

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