Electrical computers and digital data processing systems: input/ – Access arbitrating
Reexamination Certificate
2000-10-06
2003-10-14
Vo, Tim (Department: 2181)
Electrical computers and digital data processing systems: input/
Access arbitrating
C710S200000, C710S241000, C710S242000, C710S243000, C710S244000
Reexamination Certificate
active
06633938
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of digital systems and, more particularly, to reset of digital systems including two or more arbiters for a bus.
2. Description of the Related Art
A bus is frequently used in digital systems to interconnect a variety of devices included in the digital system. Generally, one or more devices are connected to the bus, and use the bus to communicate with other devices connected to the bus. As used herein, the term “agent” refers to a device which is capable of communicating on the bus. The agent may be a requesting agent if the agent is capable of initiating transactions on the bus and may be a responding agent if the agent is capable of responding to a transaction initiated by a requesting agent. A given agent may be capable of being both a requesting agent and a responding agent. Additionally, a “transaction” is a communication on the bus. The transaction may include an address transfer and optionally a data transfer. Transactions may be read transactions (transfers of data from the responding agent to the requesting agent) and write transactions (transfers of data from the requesting agent to the responding agent). Transactions may further include various coherency commands which may or may not involve a transfer of data.
The bus is a shared resource among the agents, and thus a mechanism for determining which agent is permitted to use the bus at any given time is needed. Generally, determining which of several agents is permitted to use the bus (often referred to as “mastering the bus”) is referred to as “arbitration”. An agent desiring to use the bus may signal its request to use the bus, referred to as “arbitrating”. The circuitry for performing arbitration is referred to as an “arbiter”. One or more agents may arbitrate for the bus, and the arbiter determines which of the arbitrating agents is permitted to use the bus. The agent granted use of the bus by the arbiter is referred to as the winner of the arbitration.
Arbitration may be centralized or distributed. In centralized arbitration, all arbitration requests are sent to a central arbiter which provides a grant to one of the agents. In distributed arbitration, each agent includes an arbiter which receives arbitration requests and determines the winner of the arbitration. If the agent corresponding to the arbiter is the winner, the arbiter informs the agent that it has won and that agent uses the bus. Distributed arbitration may reduce the time required from request to grant as compared to centralized arbitration, since the grant may be transmitted to the winning agent locally from the distributed arbiter at the winning agent.
In a distributed arbitration scheme, the distributed arbiters must remain synchronized with each other unless fixed priority is the arbitration policy. If synchronization is not maintained, two or more of the arbiters may signal a grant to their respective agents for the same arbitration. The agents would then simultaneously attempt to perform transactions on the bus. Such a situation is erroneous, and would lead to unpredictable results.
Additionally, it may be desirable to temporarily delay or disable access by one or more agents to the bus. For example, it may be desirable in a multiprocessing system (in which two or more processors are connected to a bus) for one of the processors to be permitted access to the bus while other processors are not permitted access. This may be useful during boot of the system, to allow the processor permitted access to read boot code from a boot read-only memory (ROM) while the other processors are held off.
Even though the agents are temporarily delayed, the arbiters corresponding to the delayed agents must remain synchronized with the other arbiters. Thus, when the agents. are subsequently permitted to use the bus, the arbiters corresponding to the agents may participate correctly in the distributed arbitration scheme.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a system as described herein. The system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a separate reset signal or signals. The arbiters are concurrently released from reset when the first reset signal is deasserted, and may have a consistent reset state to provide for synchronization of the arbiters. The agents may be independently released from reset by the separate reset signals. Accordingly, the arbiters may be synchronized and may remain synchronized even if the corresponding agents are released from reset at different times, or are temporarily held in reset for any reason. When the corresponding agents are released from reset and arbitrate, the arbiters are synchronized and arbitration may operate properly.
Providing for holding one or more agents in reset while other agents and the arbiters are operating may have a variety of uses. For example, in a multiprocessor system, one of the processors may be released from reset while the remaining processors are held in reset. The released processor may, for example, read its boot code from a boot ROM before the other processors and/or perform system initialization before the remaining processors are released. As another example, debug and testing may be simplified by allowing agents not involved in the test to be disabled. Furthermore, a defective agent may be isolated by being held in reset while other agents operate normally.
Broadly speaking, a system is contemplated. The system comprises a reset control circuit, a first agent and a second agent, and a first arbiter and a second arbiter. The reset control circuit is configured to generate a first reset signal and a second reset signal different from the first reset signal. The first agent is coupled to receive the first reset signal and configured to reset in response to an assertion of the first reset signal. The first arbiter is configured to determine if the first agent wins an arbitration for a bus, and is coupled to receive the second reset signal. The first arbiter is configured to reset in response to an assertion of the second reset signal. Coupled to receive the second reset signal and configured to reset in response to the assertion of the second reset signal, the second arbiter is configured to determine if the second agent wins an arbitration for the bus.
Additionally, in a system including (i) a first agent; (ii) a first arbiter configured to determine if the first agent wins an arbitration for a bus; (iii) a second agent; and (iv) a second arbiter configured to determine if the second agent wins an arbitration for the bus, a method is contemplated. The first agent and the second agent are reset; and the first arbiter and the second arbiter are independently reset.
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Pentium® Pro Family Developer's Manual, vol. 1: Specifications, Chapter 4, pp. 1-18, 1996.
Anderson David L.
Cho James Y.
Rowlands Joseph B.
Broadcom Corporation
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Vo Tim
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