Architecture for dynamically reconfigurable system-on-chip...
Architecture for simulation testbench control
Architecture of a chip having multiple processors and...
Arrangement for runtime compensation of a runtime difference...
Arrangement for testing a network device by interfacing a...
Arrangements for automatic re-legging of transistors
Assembly and disassembly sequences of components in...
Assertion handling for timing model extraction
Assertion handling for timing model extraction
Assessing distributed energy resources for the energynet
Associating identifiers with virtual processes
Asynchronous clock domain crossing jitter randomiser
AT-speed computer model testing methods
ATA emulation host interface in a RAID controller
ATM connection admission control device for DBR connections
Atomic coordinates generating method
Atomic transaction processing for logic simulation
Audio sample tracker
Audio signal processing apparatus
Augmenting of automated clustering-based trace sampling...