Data processing: structural design – modeling – simulation – and em – Structural design
Reexamination Certificate
1994-07-12
2001-04-17
Maung, Zarni (Department: 2758)
Data processing: structural design, modeling, simulation, and em
Structural design
C029S827000
Reexamination Certificate
active
06219627
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the architecture of multi-processor systems on a single semiconductor chip, and more particularly to such systems and methods where the several processors are interconnectable to many different memory addressing spaces.
BACKGROUND OF THE INVENTION
In the art of semiconductor chips there is a need for uniformity and modularism among chips of different processing strengths and capabilities. At first, a customer may only be able to afford chips with one or two processors and associated memories. Later, the customer may decide that because of the demands of his own customers, the system he sells needs devices with more processing capability. However, the technology of existing chips will require him to redesign his system, to accomodate more processor chips or a more powerful processor wtih a different pin-out. Thus, there is a need in the art for modular chips, that is, chips that have the majority of their pin-outs the same whether they contain one processor, or multiple processors.
In the art of semiconductor chips there is also a need for dense packing of processors and memories in a chip. The further apart a processor and an associated memory, the slower the chip. Speed in the existing technology of multi-processor, multi-memory chips is limited by the physical distance between a processor and the memory it shares with the other processors. Thus, there is a need in the art for a multi-processor, multi-memory chip that has more densely packed processors and memories.
The cross-referenced application discloses a multi-link, multi-bus, crossbar switch capable of interconnecting any processor with any memory for the interchange of data. The cross-referenced application also discloses a system which handles multi-processors having multi-memories such that the address space of all of the memories is available to one or more processors concurrently even when the processors are handling different instruction sets. However, the invention of the cross-referenced application suffers from the two deficiencies noted above in the existing technology of semiconductor chips.
The invention overcomes the above-noted and other drawbacks of the prior art by providing a method and apparatus for an integrated circuit having a chip with integrated modular parallelism wherein the integrated circuit has a majority of the same address and data pin-outs for a variable number of processors and memories on the chip.
SUMMARY OF THE INVENTION
An integrated circuit has a semiconductor chip having multiple processors and multiple memories. The chip has an architecture of the processors and memories such that there is at least first and second groups of processors and memories. The first group has at least a first processor and at least a first memory. The second group has at least a second processor and at least a second memory. Each processor is in direct communication with each memory. The architecture has modularity so that the integrated circuit has a majority of the same address and data pin-outs regardless of the number of processors on the chip. In another aspect of the invention, input/output (“I/O”) pads can be repositioned, in the design stage of the manufacturing process, to accommodate a new processor count with the same package I/O convention. In another aspect of the invention, processing elements can be easily added or removed in the design stage of the manufacturing process because of the symmetry of the “floor plan” of the integrated circuit. In another aspect of the invention, the architecture has symmetry between the groups, so that when, in the design stage of the manufacturing process, a first part of the chip is flipped over and positioned above a second part of the chip, the processors are facing each other, and the memories are facing each other, or the processors and memories are mirror images of each other.
REFERENCES:
patent: 4398248 (1983-08-01), Hsia et al.
patent: 4491907 (1985-01-01), Koepper et al.
patent: 4750113 (1988-06-01), Buggert
patent: 4807184 (1989-02-01), Shelor
patent: 4951221 (1990-08-01), Corbett et al.
patent: 4968977 (1990-11-01), Chinnaswamy et al.
patent: 4978633 (1990-12-01), Seefeldt
patent: 5144563 (1992-09-01), Date et al.
patent: 5175824 (1992-12-01), Soderbery et al.
patent: 5200908 (1993-04-01), Date et al.
patent: 5206815 (1993-04-01), Purcell
patent: 5226125 (1993-07-01), Balmer et al.
patent: 5280620 (1994-01-01), Sluijter et al.
patent: 5345228 (1994-09-01), Franaszek et al.
Patent application entitled “Multi-processor With Crossbar Link of Processors and Memories, and Method of Operation”, ser. no. 07/435,591, by Gove et al., filed Nov. 17, 1989, attorney docket number TI-14608.
Bonneau Walt C.
Gove Robert
Guttag Karl
Brady III W. James
Marshall, Jr. Robert D.
Maung Zarni
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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