Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2008-04-08
2008-04-08
Rodriguez, Paul (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07356451
ABSTRACT:
Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The assertions are viewed as part of the model, and a set of new assertions are generated automatically as part of the timing model extraction process and can be stored as part of the model. Assertions can be associated with input ports, output ports, internal pins, or hierarchical pins and can even span multiple blocks. This disclosed approach allows for application of assertions associated with timing models when the model is instantiated and detachment of assertions when the model is de-instantiated, and thus removes one of main problems associated with timing models.
REFERENCES:
patent: 5469367 (1995-11-01), Puri et al.
patent: 5508937 (1996-04-01), Abato et al.
patent: 5535145 (1996-07-01), Hathaway
patent: 5581473 (1996-12-01), Rusu et al.
patent: 5657239 (1997-08-01), Grodstein et al.
patent: 5778216 (1998-07-01), Venkatesh
patent: 5790830 (1998-08-01), Segal
patent: 5796621 (1998-08-01), Dudley et al.
patent: 5923564 (1999-07-01), Jones, Jr.
patent: 5946475 (1999-08-01), Burks et al.
patent: 6158022 (2000-12-01), Avidan
patent: 6212665 (2001-04-01), Zarkesh et al.
patent: 6247165 (2001-06-01), Wohl et al.
patent: 6421818 (2002-07-01), Dupenloup et al.
patent: 6539536 (2003-03-01), Singh et al.
patent: 6591407 (2003-07-01), Kaufman et al.
patent: 6609233 (2003-08-01), Foltin et al.
patent: 6928630 (2005-08-01), Moon et al.
patent: 2003/0009734 (2003-01-01), Burks et al.
patent: 2004/0078767 (2004-04-01), Burks et al.
patent: WO 01/08028 (2001-02-01), None
“PrimeTime Tutorial” version 1999.10, Oct. 1999, Synopsys, 89 pages.
R.G. Bushroe, S.DasGupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, Nagaraj NS, R. Steel, “Chip Hierarchical Design System (CHDS): A Foundation for Timing-driven Physical Design into the 21st Century” ISPD 1997, pp. 212-217.
Gregory A. Northrop, Pong-Fei Lu, “A Semi-Custom Design Flow in High-Performance Microprocessor Design” ACM Jun. 18-22, 2001, pp. 426-431.
David Blaauw, Rajendran Panda, Abhijit Das, “Removing user-specified false paths from timing graphs”, ACM, 2000, pp. 270-273.
Cherry, James J. , “Pearl: A CMOS Timing Analyzer”, 25thACM/IEEE Design Automation Conference, 1988, pp. 148-153.
Venkatesh, S.V. et al., “Timing Abstraction of Intellectual Property Blocks”, IEEE 1997 Custom Integrated Circuits Conference, 1997, pp. 99-102.
McDonald, Clayton B. et al., “A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells”, ICCAD, 2001, pp. 501-506.
Visweswariah, Chandu et al., “Formulation of Static Circuit Optimization with Reduced Size, Degeneracy and Redundancy by Timing Graph Manipulation”, ICCAD, 2000, pp. 244-251.
Moon, C.W. et al. “Timing Model Extraction of Hierarchical Blocks by Graph Reduction” Proceedings 2002 Design Automation Conference (IEEE Cat: No. 02CH37324) Proceedings of 39thDesign Automation Conference, New Orleans, LA, USA, Jun. 10-14, 2002, pp. 152-157.
Belkhale Krishna Prasad
Kriplani Harish
Moon Cho Woo
Bingham & McCutchen LLP
Cadence Design Systems Inc.
Craig Dwin McTaggart
Rodriguez Paul
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