Arrangements for automatic re-legging of transistors

Data processing: structural design – modeling – simulation – and em – Structural design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07079989

ABSTRACT:
Arrangements for automatic re-legging of transistors.

REFERENCES:
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John Valainis, Sinan Kaptanoglu, Erwin Liu, Robert Suaya, “Two-Dimensional IC Layout Compaction Based on Topological Design Rule Checking” IEEE 1990, pp. 260-275.
Nikolaos G. Bourbakis, Mohammad Mortazavi, “An Efficient Building Block Layout Methodology For Compact Placement” IEEE 1995, pp. 118-123.
Lack A. Feldman, Israel A. Wagner, Shmuel Wimer, “An Efficient Algorithm for Some Multirow Layout Problems”, IEEE 1993, pp. 1178-1185.

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