Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2008-04-08
2008-04-08
Rodriguez, Paul (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10313247
ABSTRACT:
Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The assertions are viewed as part of the model, and a set of new assertions are generated automatically as part of the timing model extraction process and can be stored as part of the model. Assertions can be associated with input ports, output ports, internal pins, or hierarchical pins and can even span multiple blocks. This disclosed approach allows for application of assertions associated with timing models when the model is instantiated and detachment of assertions when the model is de-instantiated, and thus removes one of main problems associated with timing models.
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Belkhale Krishna Prasad
Kriplani Harish
Moon Cho Woo
Bingham & McCutchen LLP
Cadence Design Systems Inc.
Craig Dwin McTaggart
Rodriguez Paul
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