Architecture for dynamically reconfigurable system-on-chip...

Details Architecture for dynamically reconfigurable system-on-chip... Architecture for dynamically reconfigurable system-on-chip...

2006-04-11

2010-10-19

Frejd, Russell (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Emulation

In-circuit emulator

C716S030000, C718S100000

Reexamination Certificate

active

07818163

ABSTRACT:
A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.

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