Architecture for simulation testbench control

Details Architecture for simulation testbench control Architecture for simulation testbench control

1999-06-29

2003-11-18

Broda, Samuel (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

Compatibility emulation

C703S014000

Reexamination Certificate

active

06651038

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the art of electronic circuit design. It finds particular application in conjunction with testing and/or monitoring of simulated circuits in a simulated testbench environment, and will be described with particular reference thereto. However, it is to be appreciated that the present invention is also amenable to other like applications.
In the field of electronic circuit design, it is typically advantageous to determine the manner in which a proposed circuit will respond to a given set of inputs or stimuli without having to endure the often costly and/or time consuming process of manufacturing physical prototypes for each proposed circuit design. Toward this end, software simulations have been developed that emulate a circuit under test (CUT) and test models. The test models include both drivers which apply stimuli to the CUT, and monitors which observe and/or analyze the CUT's response to the stimuli. Collectively, the CUT and test models make up a simulation testbench. Commonly, VHSIC Hardware Description Language (VHDL) is used to construct the simulation testbench (Note: VHSIC stands for Very High Speed Integrated Circuit). VHDL is an industry standard adopted in 1987 by IEEE for system modeling, documentation, simulation, and synthesis of digital and analog systems.
Previously, users were required to specifically code any interaction between test models and had to modify the connectivity of the circuit to coordinate stimuli. For example, with reference to
FIG. 1
, a prior art simulation testbench generally designated by reference numeral
10
′ includes multiple test models
12
′ which stimulate, monitor, and/or otherwise interact with a CUT
14
′. A user
16
′ separately and individually controlled each test model
12
′. A link
12
a
′ was required to tie signals from the test models
12
′ together so that they could communicate with each other, e.g., to coordinate their operations. This made synchronization difficult. To change the signal controlled interaction between the test models
12
′ required recompiling the code and, possibly, recompiling the circuit connectivity if new elements of interaction were to be included.
Additionally, much of the test model interaction was done using specific timing in the simulation. For example, at simulation time=100,000 ns the user would force a signal high which would reset two of the test models
12
′ so a particular part of the simulation would take place. Then at some time later, e.g., 110,000 ns, when certain results were expected, one of the test models
12
′ would be instructed to perform some operation such as a read operation. However, if the other test model
12
′ were later altered to perhaps include some operation prior to simulation time=110,000 ns then the synchronization is thrown off. Correction then requires re-coding of both test models.
Alternately, with reference to
FIG. 2
, a prior art simulation testbench
10
″ for testing a CUT
14
″ would employ a single monolithic test model
12
″ which incorporated all the models being used. The user
16
″ would then exercise control over the single test model
12
″. A major limitation in this case is that for simulations employing many test models the code required for the monolithic test model
12
″ become prohibitively large and unwieldy. Additionally, the lack of modularity limits the usefulness of the test model
12
″ in so much as, without extensive re-coding, it is only suited to running the simulation for which it was designed.
Accordingly, the present invention contemplates a new and improved architecture and/or technique for simulation testbench control which overcomes the above-referenced problems and others.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a simulation testbench is provided. It includes a circuit under test and a plurality of test models. The test models include at least one of a driver and a monitor. Drivers selectively apply stimuli to the circuit under test, and monitors observe responses to the stimuli from the circuit under test. A single controller is provided for the plurality of test models. The controller has an instruction source including a list of commands which control the plurality of test models. The commands are routed from the instruction source over a model control bus to the plurality of test models.
In accordance with a more limited aspect of the present invention, the controller receives responses from the plurality of test models via the model control bus.
In accordance with a more limited aspect of the present invention, a common bus interface is associated with each of the plurality of test models. The common bus interface links its associated test model to the model control bus.
In accordance with a more limited aspect of the present invention, the common bus interface accepts commands addressed to its associated test model off of the model control bus, and returns to the controller, via the model control bus, responses to the commands.
In accordance with a more limited aspect of the present invention, the common bus interface includes a test model control which: (i) signals the test model to begin an operation in accordance with the command accepted, and (ii) receives signals indicative of the test model completing the operation.
In accordance with a more limited aspect of the present invention, a sequencer addresses one command at a time from the list such that it is put out on the model control bus.
In accordance with a more limited aspect of the present invention, each command includes an operator designating an operation to be performed and a call address corresponding to a unique model address assigned to each test model. The call address designates the test model to which the command is to be routed.
In accordance with a more limited aspect of the present invention, each command further includes at least one data field which stores data employed in the operation.
In accordance with a more limited aspect of the present invention, the model control bus includes separate channels for at least the operator, the data field, and the call address.
In accordance with a more limited aspect of the present invention, the model control bus further includes separate return channels for routing responses from the plurality of test models to the controller.
In accordance with a more limited aspect of the present invention, the sequencer has a presence on the model control bus.
In accordance with a more limited aspect of the present invention, at least one separate channel on the model control bus links the sequencer with the plurality of test models.
In accordance with another aspect of the present invention, a method of controlling a simulated testbench is provided. The method includes establishing a list of commands which control a plurality of test models. From the list of commands, one is selected and put out on a model control bus where it is routed to the test model for which it is intended. From there, the command is accessed and carried out in the test model to which it was routed such that an interaction with a circuit under test is achieved.
In accordance with a more limited aspect of the present invention, the interaction involves either stimulating the circuit under test or monitoring a response from the circuit under test.
In accordance with a more limited aspect of the present invention, the step of establishing a list of commands includes storing the list of commands in an instruction source.
In accordance with a more limited aspect of the present invention, the step of establishing a list of commands involves interactively entering the commands into a controller.
In accordance with a more limited aspect of the present invention, the method further includes monitoring a response to the interaction from the circuit under test. The monitored response is then put out on the model control bus and acc

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