Data processing: structural design – modeling – simulation – and em – Emulation
Reexamination Certificate
2005-05-10
2005-05-10
Frejd, Russell (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Emulation
C370S412000, C370S395530
Reexamination Certificate
active
06892174
ABSTRACT:
A system is provided for delaying a ready signal from an emulation system, configured for emulating a network device, to a central processing unit (CPU) for initiating an access cycle of the CPU. The system includes an emulation system and a central processing unit (CPU). The emulation system is configured for operating according to an emulation clock having a maximum speed substantially less than a prescribed operating speed of the CPU. The emulation system includes programmable device configured for receiving a ready signal from the emulation system, delaying the ready signal based on the emulation clock, and sending the delayed ready signal to the CPU based on the emulation clock. The delayed ready signal enables the emulation system to complete the access cycle of the CPU prior to the CPU initiating processing of subsequent instructions.
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Paterson et al., M. Contention Resolution with Bounded Delay, 36th Annual Symposium on Foundations of Computer Science, IEEE, Oct. 1995, pp. 104-113.*
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Advanced Micro Devices , Inc.
Frejd Russell
Manelli Denison & Selter PLLC
Turkevich Leon R.
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