Layered semiconductor devices with conductive vias
Layout for a ball grid array
Lead configurations
Local interconnect using spacer-masked contact etch
Localized slots for stress relieve in copper
Localized slots for stress relieve in copper
Low capacitance interconnect structures in integrated circuits u
Low capacitance wiring layout
Low capacitance wiring layout
Low capacitance wiring layout and method for making same
Low coefficient of thermal expansion build-up layer...
Low coefficient of thermal expansion build-up layer...
Low cycle time CMOS process
Low dielectric constant material reinforcement for improved...
Low dielectric-constant dielectric for etchstop in dual...
Low resistance and inductance backside through vias and...
Low resistance contact between circuit metal levels
Low temperature aluminum reflow for multilevel metallization
Low-capacitance, plugged antifuse and method of manufacture ther
Low-leakage borderless contacts to doped regions