Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1997-12-03
2001-04-10
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S774000, C257S767000, C257S751000
Reexamination Certificate
active
06215188
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to manufacturing semiconductor devices and in particular to creating contacts and via plugs in semiconductor devices. Still more particularly, the present invention relates to an improved method for creating contacts and via plugs in semiconductor devices in which voids are minimized.
2. Description of the Related Art
Current interconnect technology employs contact and via plugs to transmit interlayer signals and interconnect lines to transmit signals along the same layer. The contact or via plugs are filled either by tungsten chemical vapor deposition (CVD) or hot aluminum physical vapor deposition (PVD). The interconnecting lines are created using PVD aluminum. Currently available hot aluminum processes for contact and via plugs involve sputter depositing by PVD a thin titanium layer (100 nm) on the substrate after the via hole is etched in the interlayer dielectric. This titanium layer provides good contact for an underlying conductor and also provides a good wetting layer for a subsequent hot aluminum process. Thereafter, the wafer is moved under vacuum to an aluminum deposition chamber in which three steps occur. First, a 200-250 nm thick nucleating layer of aluminum is deposited at a high rate of about 15 nm/s to about 20 nm/s at a low temperature to fully cover the titanium on the sidewalls and the bottom of the via. Next, the temperature of the substrate is increased to 400° C. to 550° C. More aluminum (about 400 nm) is deposited at a slower rate of about 3 nm/s. This slow deposition rate at a high temperature allows the aluminum to flow into the via as the aluminum is being deposited. This process makes use of surface diffusion to allow the aluminum to flow into the vias. Surface diffusion refers to the movement of aluminum atoms on the surface at high temperatures. Then, once the via is completely filled with aluminum, the remaining aluminum required, is again deposited at a fast rate of 15 nm/s. The wafer is then moved to a titanium nitride (TiN) deposition chamber in which a 30 nm thick TiN film is deposited. This film acts as an antireflective coating (ARC) for subsequent photolithographic processing.
Another process currently used to fill vias using aluminum involves a force fill process as disclosed in Shterenfeld-Lavie, et al.,
A Three-Level
, 0.35 &mgr;m
Interconnection Process Using an Innovative High Pressure Aluminum Plug Technology
, VMIC Conference, ISMIC-104/95/031, Pages 31-37. This method eliminates or minimizes voids within the contact or via plugs by using conventional sputtering to deposit metal films at relatively low temperatures (430° C.) and then using high pressure argon to promote metal flow into high aspect contacts on vias. This force fill method, however, requires expensive equipment to form contact and via plugs.
Therefore, it would be advantageous to have an improved method for forming via and contact plugs while minimizing voids.
SUMMARY OF THE INVENTION
The present invention provides a method for minimizing voids in a plug. The process begins by forming a conformal barrier layer within the via or contact hole and then forming a metal plug within the hole. Thereafter, a cap layer is formed over the metal plug in which the cap layer has a lower thermal expansion coefficient than the metal plug. The substrate is heated such that the metal in the via or contact hole flows to eliminate the void as a result of the compressive stress generated by the cap layer on the metal plug.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
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Z. Shterenfeld-Lavie et al, “A 3-Level, 0.35&agr;m Interconnection Process Using an Innovative, High Pressure Aluminum Plug Technology,” Proceedings of the VMIC Conf., pp. 31-37 (Jun. 27-29, 1995).
Glanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics Inc.
Thomas Tom
Tran Thien F.
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