Low cycle time CMOS process

Details Low cycle time CMOS process Low cycle time CMOS process

1997-07-14

1998-03-17

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257773, 257371, H01L 2348

Patent

active

057290563

ABSTRACT:
A process for fabricating CMOS devices has been developed, in which decreased cycle time has been achieved, via a reduction in photomasking steps. The low cycle time CMOS process features the use of only one photo mask to create both the lightly doped, as well as the heavily doped N type, source and drain regions, by performing both implantations, after creation of the insulator sidewall spacer. In addition the P type source and drain regions are formed, using an oxide layer as a blockout for the P well region, thus eliminating the use of another photomasking procedure.

REFERENCES:
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5334870 (1994-08-01), Katada et al.
Baker et al., "Transistor Design For Integrated Circuits", IBM Tech. Disc. Bull., vol. 14, No. 4, pp. 1065-1066, Sep. 1971.

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