Low-capacitance, plugged antifuse and method of manufacture ther

Details Low-capacitance, plugged antifuse and method of manufacture ther Low-capacitance, plugged antifuse and method of manufacture ther

1994-05-25

1996-05-28

Meier, Stephen D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257467, H01L 2348, H01L 2352, H01L 2940, H01L 31058

Patent

active

055214401

ABSTRACT:
An antifuse structure in an integrated circuit is provided. The antifuse structure has a first metal interconnection line and a first insulating layer over the first metal interconnection line. The first insulating layer has a via exposing a top surface of the first metal interconnection line. In the first aperture a metal plug contacts the first metal interconnection layer and has a top surface substantially coplanar with a top surface of the first insulating layer. A metal pad contacts and covers the top surface of the metal plug. The metal pad should be formed by a viscous barrier metal, such as TiW, to smooth the surface of the metal plug. A second insulating layer, relatively thin with respect to said first insulating layer, covers the metal pad and has an aperture exposing a top surface of the metal pad. A programming layer deposited over the second insulating layer and into the aperture contacts the top surface of metal pad. A second metal interconnection line rests on the programming layer. In an alternative embodiment the locations of the second insulating layer and the programming layer are reversed.

REFERENCES:
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5100827 (1992-03-01), Lytle
patent: 5106773 (1992-04-01), Chen et al.
patent: 5191241 (1993-03-01), McCollund et al.

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