Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2006-04-18
2006-04-18
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S734000
Reexamination Certificate
active
07030497
ABSTRACT:
In accordance with the objectives of the invention a new method is provided for the creation of interconnect metal. Current industry practice is to uniformly add slots to wide and long copper interconnect lines, this to achieve improved CMP results. These slots, typically having a width in excess of 3 μm and having a length in excess of 3 μm, are added to interconnect lines having a width that is equal to or in excess of 12 μm. This approach however does not, due to its lack of selectivity of location of the slots, solve problems of localized stress that are associated with isolated single vias in the metal lines. For this reason, the invention provides for the addition of one or more localized slots adjacent to isolated vias in bottom or top metal lines that are no wider than about 2 microns.
REFERENCES:
patent: 6642597 (2003-11-01), Burke et al.
Potter Roy
Taiwan Semiconductor Manufacturing Co. Ltd.
Thomas Kayden Horstemeyer & Risley
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