Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1998-10-08
2000-02-08
Loke, Steven H.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257758, 257760, H01L 2348
Patent
active
060231025
ABSTRACT:
A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. The method involves the IC processes of conformal deposition and anisotropic etching. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed with a conductive barrier lining the via sidewalls. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.
REFERENCES:
patent: 5281850 (1994-01-01), Kanamori
patent: 5559367 (1996-09-01), Cohen et al.
patent: 5661344 (1997-08-01), Havemann et al.
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5828121 (1998-10-01), Lur et al.
Hsu Sheng Teng
Nguyen Tue
Loke Steven H.
Nadav Ori
Ripma David C.
Sharp Kabushiki Kaisha
Sharp Laboratories of America Inc.
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