Low coefficient of thermal expansion build-up layer...

Details Low coefficient of thermal expansion build-up layer... Low coefficient of thermal expansion build-up layer...

2008-03-11

2008-03-11

Thai, Luan (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257SE23174, C438S637000, C438S667000, C438S672000, C438S675000

Reexamination Certificate

active

10980168

ABSTRACT:
A build-up layer packaging comprising a first ceramic substrate, a second ceramic substrate, and a circuit layer is provided. The first ceramic substrate has a through hole to dispose a die therein. The second ceramic substrate, attached to a common lower surface of the ceramic substrate and the die, further has a plurality of openings to expose the pads of the die. The openings are filled with plugs electrically connecting to the pads. The circuit layer is formed under the second ceramic substrate to transmit signals generated by the die outward.

REFERENCES:
patent: 4994902 (1991-02-01), Okahashi et al.
patent: 6111313 (2000-08-01), Kutlu
patent: 6351031 (2002-02-01), Iijima et al.
patent: 6506633 (2003-01-01), Cheng et al.
patent: 6992379 (2006-01-01), Alcoe et al.
patent: 2003/0034566 (2003-02-01), Jimarez et al.
patent: 2005/0056942 (2005-03-01), Pogge et al.

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