Simultaneous read/write cell

Single bit line SMT MRAM array architecture and the...

Single channel four transistor SRAM

Single conductor inductive sensor for a non-volatile random...

Single electron resistor memory device and method

Single ended dual port memory cell

Single ended dual port memory cell

Single ended row select for a MRAM device

Single ended row select for a MRAM device

Single ended simpler dual port memory cell

Single ended simplex dual port memory cell

Single ended transfer circuit

Single ended two-stage memory cell

Single event upset (SEU) hardened latch circuit

Single event upset (SEU) hardened static random access...

Single event upset hardened CMOS latch circuit

Single event upset hardened memory cell

Single event upset hardening CMOS memory circuit

Single event upset in SRAM cells in FPGAs with leaky gate...

Single event upset tolerant memory cell layout