Single ended two-stage memory cell

Details Single ended two-stage memory cell Single ended two-stage memory cell

2001-05-09

2003-05-06

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

Reexamination Certificate

active

06560140

ABSTRACT:

TECHNICAL FIELD
The invention relates to memory devices, specifically memory devices using a memory cell for storing data.
BACKGROUND OF THE INVENTION
A memory cell is a unit of a memory structure capable of holding at least one bit of data. A memory cell may be formed by a wide variety of methods, such as, for example, a breadboard circuit wiring using off-the-shelf electronic components or semiconductor fabrication.
Memory cells are widely used in computers and other electronic processing devices for temporary storage of data. Oftentimes, memory cells are used to repeatedly store different data values as the computer or other processing device is calculating various alternatives or seeking to obtain a solution by reviewing all possibilities.
FIG. 1
shows a flowchart of the steps performed during the transition from speculative data to permanent data. Initially, in step
101
, the microprocessor executes instructions speculatively. Speculative data is produced in step
102
. Data values determined in the course of such activities are commonly called “speculative” until the data value is determined to be the desired, final or correct result of the process. In step
103
, the final data value becomes a “permanent” or non-speculative data value. Throughout any specific series of calculations, there may be multiple segments of analysis, each ending with a permanent data value. Permanent data values are not typically stored indefinitely, and are eventually overwritten or flushed. Thus, it is determined whether the speculative data stored as permanent data is new data as shown in (step
104
). If it is determined that permanent data is new, then prior permanent data is flush as shown in (step
105
). Otherwise, the permanent is not flushed as shown in (step
106
). However, permanent data values are often retained much longer than any one of the typical series of speculative data values generated during a calculation.
Storing of a permanent data value while proceeding to generate further speculative data values is typically problematic for a conventional memory cell, in which only the last data value stored within the cell can be read. A conventional memory cell can retain only one data value and therefore is unable to retain a permanent data value while simultaneously storing a new speculative data value. Therefore, conventional applications involving storage of speculative data involve an additional memory array, or multiple memory cells within a single array, to store data desired to be retained.
The use of memory cells in the handling of multiple values of speculative data has typically involved extensive processor time, because a processor is either required to read data from a separate memory array and then write the data to another memory array or manage multiple memory cells for a single desired data value. Specifically, when a determination is made that the presently stored speculative data value
104
is no longer speculative and is desired, or permanent, data, the processor is called upon to perform multiple memory-management tasks.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a memory cell is provided having a speculative storage node adapted to store a speculative data value, a non-speculative storage node adapted to store a permanent data value and a circuit, electrically coupled to the non-speculative storage node and the speculative storage node. When the circuit is activated, the speculative data value is written to the non-speculative storage node and stored as the permanent data value.
According to another embodiment of the invention, a memory cell is provided having an array structure. The memory array is also provided with a two-stage memory cell having a speculative storage node, a non-speculative storage node, and a circuit. The two-stage memory cell is electrically coupled to the array structure. Activation of the circuit causes a speculative data value stored in the speculative storage node to be written to the non-speculative storage node.
According to another embodiment of the invention, a memory array is provided having an array structure that has at least one memory cell, including a word write bit line and a single transfer line. The memory array is also provided with a two-stage memory cell having a speculative storage node, a non-speculative storage node, and a circuit. The two-stage memory cell is electrically coupled to the array structure. Activation of the circuit causes a speculative data value stored in the speculative storage node to be written to the non-speculative storage node.


REFERENCES:
patent: 4651303 (1987-03-01), Dias et al.
patent: 6118690 (2000-09-01), Jiang et al.
patent: 6353552 (2002-03-01), Sample et al.
U.S. patent application Ser. No. 09/852,429, Staraitis et al., filed May 9, 2001.

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