Single bit line SMT MRAM array architecture and the...

Static information storage and retrieval – Systems using particular element – Magnetic thin film

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S158000

Reexamination Certificate

active

07957183

ABSTRACT:
An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receiving an out-of-phase data signal. Out-of-phase switching devices are connected to the source lines for selectively transferring the out-of-phase signal to the at least one source lines. Column select transistors are connected to the single bit lines for transferring an in-phase data signal to a selected column of the SMT MRAM cells. A precharge circuit selectively charges or discharges the single bit lines. Ground switching devices selectively connect to the source lines to a ground reference voltage source. A method for programming a selected SMT MRAM cell within a provided SMT MRAM device is described.

REFERENCES:
patent: 7272034 (2007-09-01), Chen et al.
patent: 7286395 (2007-10-01), Chen et al.
patent: 7379327 (2008-05-01), Chen et al.
patent: 7443718 (2008-10-01), Ito et al.
patent: 7884433 (2011-02-01), Zhong et al.
patent: 2007/0097730 (2007-05-01), Chen et al.
patent: 2007/0285975 (2007-12-01), Kawahara et al.
patent: 2007/0297223 (2007-12-01), Chen et al.
patent: 2008/0061388 (2008-03-01), Diao et al.
“A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Swithcing: Spin-RAM,” by M. Hosomi et al., 2005 IEEE, 0-7803-9269-8/05, 4 pages.
“2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Road,” by Takayuki Kawahara et al., IEEE Journal of Solid-State Circuits, vol. 43, No. 1, Jan. 2008, pp. 109-120.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Single bit line SMT MRAM array architecture and the... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single bit line SMT MRAM array architecture and the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single bit line SMT MRAM array architecture and the... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2666135

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.