Single event upset hardened memory cell

Details Single event upset hardened memory cell Single event upset hardened memory cell

1988-09-07

1990-03-27

Moffitt, James W.

Static information storage and retrieval

Systems using particular element

Flip-flop

G11C 1140

Patent

active

049126750

ABSTRACT:
Single event upset hardening is provided in a static random access memory cell, including cross-coupled inverters, by the restoration of voltages at selected nodes within the cell by a pair of transistors connected to the cross-coupling between inverters.

REFERENCES:
patent: 4725981 (1988-02-01), Rutledge
patent: 4797804 (1989-01-01), Rockett, Jr.
"CMOS RAM Cosmic Ray-Induced Error Rate Analysis", J. C. Pickel, et al. IEEE Trans. on Nuclear Science, vol. NS-28, pp. 3962-3967 (1981).
"DMSP Dosimetry Data: A Space Measurement and Mapping of Upset Causing Phenomena", E. G. Gussenhower, et al., IEEE Trans. Nuclear Science, vol. NS-34, pp. 1251-1255 (1987).
"An SEU Tolerant Memory Cell Derived from Fundamental STudies of SEU Mechanisms in SRAM", H. T. Weaver, et al., IEEE Trans. Nuclear Science, vol. NS-34, pp. 1281-1286 (1987).
"Alpha Particle Induced Soft Errors in Dynamic Memories", T. C. May, et al., IEEE Trans. Electronic Devices, vol. ED-26, p. 2 (1979).

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