Single channel four transistor SRAM

Details Single channel four transistor SRAM Single channel four transistor SRAM

2001-02-14

2002-08-27

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S188000, C365S156000

Reexamination Certificate

active

06442061

ABSTRACT:

FIELD
This invention relates to the field of integrated circuits. More particularly this invention relates to the field of reducing the size of monolithic, semiconductor static random access memory circuits.
BACKGROUND
Integrated circuit designers continually look for ways in which to reduce size of individual integrated circuits. By so doing, an additional number of integrated circuits may be formed in a given surface area of material. Thus, devices of the same size are able to increase in capacity, and typically do so with a decrease in cost, or at least a decrease in the cost per integrated circuit contained within the device.
Unfortunately, many structures within an integrated circuit are not easily reduced in size, or have already been reduced in size to a minimum practical limit given current technology. For example, the surface area of a substrate required for a six transistor CMOS memory cell has already been reduced to a significant degree. Current technology makes a further reduction in the size of a six transistor CMOS memory relatively difficult, to the point that any further reduction in size may come at the cost of increased expense of manufacture per memory cell, rather than enjoying a decreased expense of manufacture per memory cell.
What is needed therefore, is a smaller memory cell that can be fabricated using currently available processes and at relatively reduced expense.
SUMMARY
The above and other needs are provided by a method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line.
A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line.
A first state node transistor is also formed of the first transistor type. The first state node transistor has a gate oxide with a second thickness. The source of the first state node transistor is electrically connected to the first state node, and the drain of the first state node transistor is electrically connected to a ground line. The gate of the first state node is electrically connected to the second state node.
A second state node transistor is also formed of the first transistor type. The second state node transistor also has a gate oxide with the second thickness. The source of the second state node transistor is electrically connected to the second state node, and the drain of the second state node transistor is electrically connected to the ground line. The gate of the second state node is electrically connected to the first state node.
In various preferred embodiments, the first thickness of gate oxide is greater than the second thickness of gate oxide, and the first transistor type may be alternately NMOS or PMOS.
By having only four transistors in the memory cell instead of six, the size of the memory cell is reduced considerably. Further, but not having a separate load on the sources of the first state node transistor and the second state node transistor, the size of the memory cell is further reduced. Finally, by forming the first pass gate transistor and the second pass gate transistor with a different thickness of gate oxide, the first pass gate transistor and the second pass gate transistor can be formed with a leakage current that is much greater than the first state node transistor and the second state node transistor, which enables the memory cell to be formed of transistors that are all of the same type. In traditional memory cell architecture, either a load is preferably applied to the sources of the first state node transistor and the second state node transistor, or the first state node transistor and the second state node transistor are preferably formed of a different transistor type than the first pass gate transistor and the second pass gate transistor.
For example, typically when no load is provided, both the first state node transistor and the second state node transistor are formed as NMOS transistors and both the first pass gate transistor and the second pass gate transistor are formed as PMOS transistors. Alternately, both the first state node transistor and the second state node transistor are formed as PMOS transistors and both the first pass gate transistor and the second pass gate transistor are formed as NMOS transistors. In either configuration, isolation structures are typically required to isolate the PMOS transistors from the NMOS transistors. These isolation structures tend to require additional surface area in the substrate in which the memory cell is formed, and thus act to generally increase the resultant size of the memory cell. However, according to the present invention, traditional isolation structures are not required because the transistors may all be formed of the same transistor type, whether PMOS or NMOS. Thus, memory cells according to the present invention tend to require less surface area than memory cells in the prior art.
Additionally, by forming the first pass gate transistor and the second pass gate transistor with a greater thickness of gate oxide than the first state node transistor and the second state node transistor, the first pass gate transistor and the second pass gate transistor can selectively receive and pass a voltage potential that is greater than would otherwise be advisable for a thinner gate oxide device, and thus can store a commensurately greater voltage potential on the first state node and the second state node. Thus, the first state node and the second state node can store a full voltage potential according to the preferred voltage of the first state node transistor and the second state node transistor, rather than a voltage potential that is somewhat less than a full state voltage potential. This operational configuration further reduces any need for pull up transistors or loads.
In additional preferred embodiments, a single well contains all of the first pass gate transistor, the second pass gate transistor, the first state node transistor, and the second state node transistor. Most preferably, the leakage current of the first pass gate transistor and the second pass gate transistor is about one hundred times the leakage current of the first state node transistor and the second state node transistor. The thickness of the gate oxide for both the first pass gate transistor and the second pass gate transistor is preferably about sixty angstroms, with a channel length of about 0.24 microns, and a width of about 0.3 microns. It is appreciated that these numbers will preferably scale with other dimensions as the overall size of the memory cell is generally reduced.


REFERENCES:
patent: 5068825 (1991-11-01), Mahant-Shetti et al.
patent: 5640342 (1997-06-01), Gonzalez
patent: 5881010 (1999-03-01), Artieri
patent: 6172899 (2001-01-01), Marr et al.
patent: 6285578 (2001-09-01), Huang
patent: 6301146 (2001-10-01), Ang et al.
Takeda et al., A 16Mb 400MHz Loadless CMOS Four-Transistor SRAM Macro, 2000 IEEE International Solid-State Circuits Conference, pp. 264-265 and supplement 212-213, IEEE, Feb. 8, 2000.
Noda et al., A 1.9-&mgr;m2Loadless CMOS Four-Transistor SRAM Cell in a 0.18-&mgr;m Logic Technology, IEDM 98, pp. 643-646, IEEE, 1998.
Imai et al., CMOS device optimization for system-on-a-chip applications, IEEE, 2000.
Noda et al., An Ultra-High-Density High-Speed Loadless Four-Transistor SRAM Macro with a Dual-Layered Twisted Bit-

Affiliated with

Also associated with

Rating

Single channel four transistor SRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single channel four transistor SRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single channel four transistor SRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2920171