Single event upset (SEU) hardened latch circuit

Details Single event upset (SEU) hardened latch circuit Single event upset (SEU) hardened latch circuit

2001-04-26

2001-12-04

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000

Reexamination Certificate

active

06327176

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to integrated circuits in general, and in particular to latch circuits. Still more particularly, the present invention relates to a single event upset hardened latch circuit.
2. Description of the Prior Art
Most, if not all, electronic products use latch circuits to store data during data processing operations. Latch circuits are bistable devices having output signals assuming one of two stable states based on a signal level or signal transition of an input signal. Conventional latch circuits include dynamic and static latch circuits. Compared to static latch circuits, dynamic latch circuits typically require less circuitry and operate faster. However, electrical charges stored in dynamic latch circuits tend to dissipate over time through current leakage and thus, dynamic latch circuits disadvantageously require regular charge refresh in order to maintain proper stored signal level. Even though the signal level maintained by static latch circuits do not change over time, standard static latch circuits are still susceptible to single event upsets. Thus, standard static latch circuits may not be very suitable for applications in an environment having high levels of radiation, such as aerospace applications.
An integrated circuit device is said to be radiation hardened if it can continue to function within specifications after exposure to a specified amount of radiation. While it is possible to construct a radiation hardened integrated circuit device with radiation shields in order to achieve the radiation tolerant requirements for aerospace systems, such approach tends to undesirably increase weight, expense, and complexity to the circuit design within such systems. Consequently, it is desirable to provide an improved latch circuit that is radiation hardened to be utilized in high-radiation environments.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.
In accordance with an alternative embodiment of the present invention, a single event hardened latch circuit includes a dual-port inverter for receiving a first input, and a dual-port logic NOR gate for receiving a second input. The first input is coupled to the dual-port inverter via a first set of pass gates. The dual-port logic NOR gate is coupled to the dual-port inverter via a second set of pass gates. An output connected to the dual-port inverter and the dual-port logic NOR gate.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 5905290 (1999-05-01), Houston
patent: 5940318 (1999-08-01), Bessot
patent: 6005797 (1999-12-01), Porter et al.
patent: 6111780 (2000-08-01), Bertin
patent: 6215694 (2001-04-01), Li et al.

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