Single-chip synchronous dynamic random access memory (DRAM) syst

Single-clock, strobeless signaling system

Single-clock, strobeless signaling system

Single-clock, strobeless signaling system

Single-clock, strobeless signaling system

Single-clock, strobeless signaling system

Single-clock, strobeless signaling system

Slew tolerant clock input buffer and a self-timed memory...

SRAM device capable of performing burst operation

SRAM emulator

SRAM synchronized with an optimized clock signal based on a...

SRAM-address-change-detection circuit

Staggered pipeline access scheme for synchronous random access m

Staggered pipeline access scheme for synchronous random access m

State maintenance pulsing for a memory device

State maintenance pulsing for a memory device

Static memory containing sense AMP and sense AMP switching circu

Static memory device provided with a signal generating circuit f

Static memory utilizing transition detectors to reduce power con

Static random access memory device with power down function