Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-07-06
2003-11-11
Lam, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S240000, C365S189120, C365S194000
Reexamination Certificate
active
06646953
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to communication systems, and more particularly to apparatus and methods for high speed signaling.
ART BACKGROUND
In systems which require high speed transmission of data between two or more integrated circuit devices, it is common for a timing signal to be transmitted in parallel with the data signal. By this arrangement, sometimes referred to as “source synchronous timing,” the timing and data signals experience similar propagation delays, providing the receiving device with a timing reference having a controlled phase relationship with the data signal. Circuitry within the receiving device samples the incoming data signal at a time determined by the timing signal and its phase relationship with the data signal.
FIGS. 1A and 1B
illustrate prior-art memory systems that use variants of source-synchronous timing. In the system of
FIG. 1A
, a folded clockline
12
is used to carry a clock signal toward a controller
10
on a first segment of the clockline and away from the controller on a second segment of the clockline. The clock signal is generated by a clock generator
18
. Each of the memory devices
14
includes a pair of clock inputs coupled respectively to the two segments of the folded clockline. The memory devices transmit information to the controller on a data/control path
16
in a fixed phase relationship with the clock signal as it propagates toward the controller on the first clockline segment, and receive information from the controller via the data/control path according to a fixed phase relationship between the information and the clock signal propagating away from the controller on the second clockline segment. Typically, the controller is coupled to the clockline at the fold so that the timing references that it uses for transmit and receive are in phase. By providing source synchronous timing references in this way, timing skew problems that plague other types of high-speed signaling systems are avoided.
In the memory system of
FIG. 1B
, the memory devices
20
are coupled to a memory controller
21
via respective data paths
23
and also via respective pairs of strobe paths
24
. A clock generator
22
is used to provide a frequency reference to the memory controller and each of the memory devices. In operation, the memory controller asserts a strobe signal on one of the pair strobe paths to provide a timing reference for transmission of data to a memory device, and a memory device asserts a strobe signal on the other of the pair of strobe paths to provide a timing reference for transmission of data to the controller. Typically, strobe signal paths are routed and conditioned to equalize the propagation times between strobe signals and corresponding data transmissions. Consequently, the strobe signals constitute source synchronous timing references that facilitate high-speed signaling without timing skew.
One disadvantage of the prior art systems of
FIGS. 1A and 1B
is that additional pins are required on the memory controller and slave devices, and additional traces are required on the circuit board to support transmission of the source synchronous timing references. The proliferation of traces is particularly problematic in the system of
FIG. 1B
, because the number of strobe paths is a multiple of the number of memory devices. Consequently, the routing of timing and data paths in such systems is often complex, involving a dozen or more circuit board layers.
Another disadvantage of the prior art systems of
FIGS. 1A and 1B
is the additional layout complexity that results from the need to equalize the electrical lengths of the timing and data paths to avoid skew between the timing and data signals. Electrical length equalization is particularly challenging in view of the fact that the data path is typically a multi-conductor path having a higher parasitic capacitance than the timing reference paths. Again, the large number of strobe paths required in the system of
FIG. 1B
further complicates matters. Numerous passive devices are often used for electrical length equalization in such systems, necessitating additional printed circuit board layers.
SUMMARY OF THE INVENTION
A single-clock, strobeless signaling system is disclosed. In one embodiment, the signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path. Various alternative embodiments of the signaling system are disclosed as are embodiments of master and slave devices and methods for operating the same.
REFERENCES:
patent: 5809263 (1998-09-01), Farmwald et al.
patent: 5923611 (1999-07-01), Ryan
patent: 6016282 (2000-01-01), Keeth
patent: 6026050 (2000-02-01), Baker et al.
patent: 6029250 (2000-02-01), Keeth
patent: 6029252 (2000-02-01), Manning
patent: 6031787 (2000-02-01), Jeddeloh
patent: 6094704 (2000-07-01), Martin et al.
patent: 6094727 (2000-07-01), Manning
patent: 6101197 (2000-08-01), Keeth et al.
patent: 6101612 (2000-08-01), Jeddeloh
patent: 6108795 (2000-08-01), Jeddeloh
patent: 6510503 (2003-01-01), Gillingham et al.
patent: 2000307421 (2000-09-01), None
patent: WO 01/29680 (2001-04-01), None
Yoon et al., “A 2.5V 333Mb/pin 1Gb Double Data Rate SDRAM”, ISSCC Digest of Technical Papers, pp. 412-413, Feb. 17, 1999.
Peter Gillinghan & Bill Vogley, “SLDRAM: High-Performance Open-Standard Memory,” IEEE Micro, Nov./Dec. 1997, pp. 29-39, vol. 17, No. 6, Institute of Electrical and Electronics Engineers, Inc. Los Alamitos, California.
SLDRAM Inc., “SLD4M18DR400 4 MEG×18 SLDRAM: 400 Mb/s/pin SLDRAM 4M×18 SLDRAM Pipelined, Eight Bank 2.5 V Operation,” Jul. 9, 1998, pp. 1-69, SLDRAM Inc., San Jose California.
Lam David
Rambus Inc.
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