Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-07-11
2001-08-07
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230060
Reexamination Certificate
active
06272067
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to electronic memories and more specifically to synchronous Static Random Access Memory design.
2. Description of Related Art
Static Random Access Memory (SRAM) is a type of electronic memory that is faster and more reliable than the more common Dynamic Random Access Memory (DRAM). The term “static” is derived from the fact that SRAM does not need to be refreshed like DRAM. As long as SRAM memory is supplied power, it will retain its memory.
SRAM is often used as cache memory. Some cache memories are built into microprocessors. The Intel® 80486 microprocessor, for example, contains an 8K memory cache, and the Pentium® microprocessor contains a 16K cache. Such internal caches are often called Level 1 (L1) caches. Many modern PCs also come with external cache memory, called Level 2 (L2) cache. These caches reside between the CPU and the DRAM. Like L1 caches, L2 caches are composed of SRAM but are typically much larger.
Regardless of how an SRAM chip is implemented, the architecture is somewhat standard. All SRAM chips contain an array of memory cells. A memory cell stores a single bit of information (1 or 0). Peripheral circuits control how each memory cell is accessed. A unique address refers to either a single bit or a group of bits, depending upon the architecture of the SRAM chip. All references to a “set of memory cells” shall mean the set of bits stored in one address location, regardless of whether the number of bits is singular or plural.
Synchronous SRAM uses a clock signal to time the phases of operation of the SRAM circuit. For active-high logic circuits, the pre-charge phase (“PC phase”) is performed during the high portion of the clock signal and the access phase (“AC phase”) during the low portion. The phases of an active-low circuit are performed in the opposite clock states. Although the circuits described herein will assume active-high logic, those skilled in the art will be able to apply the concepts to either active-high or active-low circuitry.
During the PC phase, the memory array pre-charges, the address is decoded and the decision of whether to read or write is made. The AC phase is when the actual reading or writing to the memory cell is performed. Since both phases are necessary, only one complete read or write operation can be performed during a full clock period for a standard six transistor SRAM chip.
The cost effectiveness of synchronous SRAM depends partly upon the speed of the clock signal. A system with a clock signal that remains in its high state for longer than is needed to complete the PC phase is inefficient. Similarly, it is inefficient for an SRAM chip to remain in its AC phase for longer than is required while the clock signal is low. The speed of a system clock is usually selected based on the requirements of the processor rather than being selected to optimize operation of an SRAM chip.
Direct Memory Access (DMA) is a technique for transferring data from main memory to a CPU without passing it through a memory management system. A DMA request could occur at either the first half or the second half of a clock cycle. If a DMA request were received in the second half of a clock cycle, a prior art synchronous SRAM chip would not be able to process the request until the next clock cycle.
Additionally, since the majority of SRAM chips are single port chips that only allow one memory access at a time, the microprocessor would be required arbitrate DMA requests. The microprocessor would grant a DMA request by pausing its own use of the memory while allowing the device requesting the DMA to access the memory. Although dual port memory chips are available, they are far too large and costly to be used regularly.
What is needed is a synchronous SRAM chip that overcomes shortfalls of the SRAMs currently known in the art.
BRIEF SUMMARY OF THE INVENTION
The present invention provides an improved SRAM chip synchronized with an external periodic signal and a method for constructing the same. The SRAM chip includes a memory array, control circuitry, an address decoder, pre-charge circuitry, read circuitry and write circuitry. The memory array consists of a plurality of memory cells and their associated bit lines and word lines. The control circuitry is operably connected with and regulates the operation of the memory cells. The “control time” is equal to the interval required for the control circuitry to complete its most time-consuming operation. The address decoder can select any memory cell in the memory array within an “address time.” The pre-charge circuitry charges the bit lines of the memory array to a high state within a “pre-charge time.” The “critical PC time” is equal to the longest of the control time, the address time or the pre-charge time. The read circuitry receives signals from the bit lines of the memory cells. The write circuitry replaces the signals stored by the memory cells. The most time consuming operation can be completed in a “read time” for the read circuitry and a “write time” for the write circuitry. The “critical AC time” is the time interval equal to the greater of the read time or the write time. A signal optimizer is operably connected to the control circuits and is capable of receiving the external periodic signal and transforming that signal into a higher frequency signal that maintains its high state for at least the critical PC time and its low state for at least the critical AC time.
The method for designing the improved SRAM chip synchronized with an external clock signal according to the present invention begins with designing a preliminary architecture of an SRAM chip including a plurality of memory cells and peripheral circuits. A critical PC time, a critical AC time, and an optimization factor must be determined. The critical PC time is determined from the worst-case scenario circuit in the PC phase, namely the operation that requires the most time to execute during the PC phase. The critical AC time is determined from the worst-case scenario circuit in the AC phase. The optimization factor is a number representing how many times the critical PC time added to the critical AC time will divide into the period of an external clock cycle. An optimization circuit must be designed that can receive a system clock signal as an input and output an optimized clock signal that has a frequency equal to the optimization factor times the frequency of the system clock signal. Additionally, the optimized clock signal must remain in its active state for at least the critical PC time and in its inactive state for at least the critical AC time.
An advantage of the present invention is that a synchronous SRAM chip can access its memory array multiple times during one clock cycle.
A feature of the invention is that a response to a DMA request can occur within the same system clock cycle the DMA was received.
A feature of the invention is that a microprocessor does not need to pause its own access to memory while a DMA request is being granted.
These and other objects, advantages, and features of this invention will be apparent from the following description.
REFERENCES:
patent: 5930523 (1999-07-01), Kawasaki et al.
Lee Eric W.
Nguyen Huy
Sun Bruce C.
Carr & Ferrell LLP
Le Vu A.
Malino Morgan E.
Rosun Technologies, Inc.
LandOfFree
SRAM synchronized with an optimized clock signal based on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with SRAM synchronized with an optimized clock signal based on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM synchronized with an optimized clock signal based on a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2485500