State maintenance pulsing for a memory device

Details State maintenance pulsing for a memory device State maintenance pulsing for a memory device

2008-05-27

2008-05-27

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S200000

Reexamination Certificate

active

07379381

ABSTRACT:
State maintenance of a memory cell and, more particularly, state maintenance pulsing of identified memory cells more frequently than other memory cells, is described. A memory array includes an array of memory cells. State maintenance circuitry is coupled to the array of memory cells. The state maintenance circuitry is configured to select between a first restore address and a second restore address. In a given operation cycle, the first restore address is associated with a first line in the array of memory cells, and the second restore address is associated with a second line in the array of memory cells. The first line has first memory cells coupled thereto. The second line has second memory cells coupled thereto. The first memory cells are capable of passing a threshold retention time with a first frequency of restore cycling. The second memory cells are capable of passing the threshold retention time with a second frequency of restore cycling. The second frequency of restore cycling is greater than the first frequency of restore cycling.

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