Slew tolerant clock input buffer and a self-timed memory...

Details Slew tolerant clock input buffer and a self-timed memory... Slew tolerant clock input buffer and a self-timed memory...

2000-06-15

2001-04-24

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S190000, C327S212000, C327S217000

Reexamination Certificate

active

06222791

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to apparatus for improved memory self-timing circuitry.
2. Description of the Related Art
Modem computers typically include one or more memory units for storing data. Among a variety of memory devices, random access memory (RAM) is widely used to allow storage of data and access to the stored data. Conventional RAM units such as DRAM, SRAM, RDRAM, and SDRAM typically include semiconductor memory cores for storing data. These semiconductor memory cores are usually laid-out in array format, such that each individual core cell is coupled by a wordline and a pair of differential bitlines. To access data stored in a selected core cell, associated memory accessing circuitry is commonly designed around a memory core. For example, some of the key memory accessing circuitry typically includes addressing circuitry for selecting a core cell, wordline drivers for driving a selected wordline, and sense amplifiers for amplifying the signal read from the selected core cell. Memory cores and associated memory accessing circuitry are well known in the art and are described, for example, in U.S. patent application Ser. No. 08/956,981, filed Oct. 24, 1999, entitled “High Speed Memory Self-timing Circuitry and Methods for Implementing the Same,” now U.S. Pat. No. 5,999,484, which is incorporated herein by reference.
Today's high speed memories are typically self-timed. For example, a memory performs an I/O operation in response to a rising or falling edge of a clock. Upon completion of the operation, the memory generates a reset signal and enters into a reset state (e.g., precharge state) to wait for another I/O operation.
FIG. 1A
shows a schematic block diagram of a self-timed memory device
100
having a memory core
102
and an SR latch
104
. The memory core
102
includes a plurality of core cells (not shown) that are laid out in an array format throughout the memory core
102
. The SR latch
104
receives an external clock CLK and a reset signal RESET as inputs. The SR latch
104
generates a global timing pulse (GTP) at its output port. The memory core
102
receives the GTP signal from the clock input buffer
104
for performing an I/O operation such as a read or write operation. Upon completion of the I/O operation, the control circuitry
106
in the memory core
102
generates a RESET signal indicating completion of the I/O operation. The RESET signal is then provided to the SR latch
104
for resetting the latch
104
.
FIG. 1B
illustrates a timing diagram
110
of the operation of the self-timed memory device
100
in more detail. In this diagram
110
, a rising edge of CLK at time T1 triggers or sets the SR latch
104
to output a high state for GTP at time T2. In response to the GTP, the memory core performs an I/O operation and upon completion, activates RESET high at time T3. The RESET signal then causes the SR latch
104
to reset, which in turn causes GTP signal to go low at time T4. The low GTP signal then causes the memory core
102
to set RESET signal to low at time T5.
Often, however, the CLK may remain in the high state for a longer period of time. For example, as shown in
FIG. 1B
, the CLK is high from T1 to T5. In this case, the set signal (CLK) and RESET signal are both high, which leads to unstable conditions in the SR latch. Furthermore, when the latch
104
is reset before CLK transitions to low, the memory core
102
may be triggered again when no I/O operation is actually being performed. Hence, the memory core
102
may be triggered multiple times in a single CLK cycle.
To remedy such conditions, conventional self-timed memory devices have implemented one-shot circuits.
FIG. 1C
shows a conventional one-shot
122
coupled to the SR latch
104
at the front end. The one-shot
122
includes an AND gate
124
and an inverter
126
. The AND gate
124
and the inverter
126
both receive CLK as inputs. The inverter
126
inverts CLK and provides inverted {overscore (CLK)} to the AND gate
124
. In this process, the inverter
126
introduces a delay to the inverted signal {overscore (CLK)}. In response to the CLK and delayed {overscore (CLK)} signals, the AND gate
124
generates a signal SET that is fed into the SR latch
104
.
FIG. 1D
illustrates a timing diagram
130
of the one-shot
122
in operation. Initially, when CLK is low, its inverse {overscore (CLK)} is high in a steady state. Thus, when CLK transitions from low to high at time T1, both CLK and {overscore (CLK)} are high until time T3. The rising edge of CLK at time T1 causes signal SET to transition from low to high at time T2. In addition, the rising edge of CLK also causes {overscore (CLK)} to transition from high to low at time T3. The interval between T1 and T3 corresponds to the delay associated with the inverter
126
. The transition of {overscore (CLK)} at T3 causes the SET signal to go low at time T4. By thus triggering SET to transition low, the one-shot
122
prevents multiple triggering the memory core
102
in a single cycle.
The use of one-shot
122
, however, has several drawbacks. For example, the one-shot
122
generally requires a sufficiently long delay to set the SR latch
104
. This is because the SET must be in high state long enough for the GTP at the output of the SR latch
104
to go high. If the delay associated with the inverter
126
is too short, SET may not be high long enough for the SR latch
104
to output a high state for GTP. In such cases, the SR latch
104
must wait for the SET signal to go high again before triggering the memory core
102
. Accordingly, the speed of the memory operations through the memory core
102
may be compromised significantly.
On the other hand, if the delay is too long, it can leak into the next cycle.
FIG. 1E
shows a timing diagram
150
for the one-shot
122
when a delay D is too long. Initially, CLK is low and {overscore (CLK)} is high at steady state. Then, at time T1, CLK transitions from low to high. This CLK transition causes SET to transition from low to high at time T2. Likewise, the CLK transition at T1 also causes {overscore (CLK)} to transition from high to low at time T4. The transition of {overscore (CLK)} at T4 triggers SET to go low at time T5. In the meantime, CLK transitions from high to low at time T3, which triggers {overscore (CLK)} to go high at time T7. The time interval between T4 and T6 or T2 and T5 corresponds to the delay D.
The transition of {overscore (CLK)} at T7, in turn, causes SET to go high at time T8. Due to the long delay D, however, {overscore (CLK)} has not transitioned to a high state before the next rising edge of CLK at time T6. As can be appreciated, such timing irregularity adversely affects the performance of the memory device
100
. Furthermore, the slew rate of CLK that is provided to the one-shot may vary over a wide range and may adversely impact the performance of the memory device
100
. For example, if the CLK slew rate is too long, one-shot
122
may not be able to trigger SET sufficiently high to trigger the SR latch
104
.
Thus, what is needed is a clock input buffer that provides optimum delay to a selftimed memory core to speed up memory access operations without triggering the memory core a multiple times in a cycle. In addition, there is a need for a clock input buffer that can efficiently operate with over a wide range of clock slew rates without compromising memory performance.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a clock input buffer for a self-timed memory core that provides optimum delay for speeding up memory access operations. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several embodiments of the p resent invention are described below.
In one embodiment, the present invention provides a clock input buffer for a self-timed memory core that is configured to st

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