Flip-flop with metastability reduction
Flip-flop with transmission gate in master latch
Flip-flop, frequency divider and RF circuit having the same
Flip-flops
Flip-flops, shift registers, and active-matrix display devices
Flip-flops, shift registers, and active-matrix display devices
Flipflop that can tolerate arbitrarily slow clock edges
Frequency divider system
Fully differential double edge triggered flip-flop
Gate driver circuit and hysteresis circuit therefor
Gated clock flip-flops
Generation of true and complement signals in dynamic circuits
Hi-speed and low-power flip-flop
High hysteresis width input circuit
High performance dynamic logic compatible and scannable transpar
High performance energy efficient push pull D flip flop circuits
High performance impulse flip-flops
High performance impulse flip-flops
High performance state saving circuit
High performance, low power differential latch