Generation of true and complement signals in dynamic circuits

Details Generation of true and complement signals in dynamic circuits Generation of true and complement signals in dynamic circuits

1997-07-14

2000-04-18

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327211, 326 98, H03K 19096

Patent

active

060520086

ABSTRACT:
A logic circuit includes an inverter for generating a complement of an output signal from another logic circuit for input to a dynamic logic circuit. The dynamic logic circuit is capable of receiving both the complement signal and dynamic input signals during both the precharge and evaluate phases of the dynamic logic circuit. The complement signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages with the dynamic logic circuit still capable of correctly evaluating the implemented logical operation of the dynamic logic circuit on the complement signal and the dynamic input signals. A p-channel FET is coupled between the internal precharge node and a voltage reference source where the gate electrode of the p-channel FET device receives the complement signal. Such a configuration eliminates the need for duplicate circuitry necessary to generate the complement signal for use by the dynamic logic circuit and also eliminates the addition of clock skew necessary to prevent potential false switching when using a complement signal generated by simple inversion.

REFERENCES:
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patent: 5117133 (1992-05-01), Luebs
patent: 5148391 (1992-09-01), Zagar
patent: 5821775 (1998-10-01), Mehta et al.
patent: 5867038 (1999-02-01), Kartschoke et al.
"Power Saving latch", IBM Technical Disclosure Bulletin, vol. 39, No. 04, Apr. 1996, pp. 65-66.

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