Hi-speed and low-power flip-flop

Details Hi-speed and low-power flip-flop Hi-speed and low-power flip-flop

1992-10-05

1995-01-24

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327212, 327215, 326 95, H03K 3356, H03K 3289

Patent

active

053844939

ABSTRACT:
A semiconductor integrated circuit comprises a pair of complementary groups of MOS transistors disposed between first and second reference potentials and switched on and off through a pair of complementary groups of input signals inputted to gates thereof, a first switching transistor switched on and off by a clock signal, and a pair of cross-connected second switching transistors disposed between the reference potentials and connected with the pair of groups of MOS transistors. With this construction, unlike prior art techniques, the semiconductor integrated circuit of the present invention operates with greater speed and reduced power consumption, without increasing the channel width of the constituent transistor, and without the need for an inverted clock signal.

REFERENCES:
patent: 3610965 (1971-10-01), Martin
patent: 4039960 (1977-12-01), Clark
patent: 4438351 (1984-03-01), Schuermeyer
patent: 4851710 (1989-07-01), Grivna
patent: 5036217 (1991-07-01), Rollins et al.
patent: 5192333 (1993-03-01), Nakano
patent: 5245223 (1993-09-01), Lim et al.
Y. Suzuki, "Clocked CMOS Calculator Circuitry", IEEE, Journal of Solid-State Circuits, vol. SC-8, No. 6, Dec. 1973, pp. 462-469.
Heller et al., "Cascade Voltage Switch Logic: A Differential CMOS Logic Family", 1984 IEEE International Solid-State Circuits Conference, Feb. 22, 1984, pp. 16-17.

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