Gated clock flip-flops

Details Gated clock flip-flops Gated clock flip-flops

1999-06-02

2001-08-14

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S207000

Reexamination Certificate

active

06275081

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuits and more particularly concerns the use of integrated logic circuitry that can be implemented in the efficient testing of integrated circuit designs.
2. Description of the Related Art
Electronic devices, such as computer chips, can include thousands upon thousands of logic circuits. To ensure that the logic circuits are operating correctly before they are put to use, these circuits are tested to verify wiring and timing integrity. To facilitate this testing, during fabrication flip-flops are configured with multiplexers to form scan-flops. Usually, many scan flops are linked together throughout the IC design to form a chain of scan flops. A scan flop chain, therefore, will enable operation in both a test mode and a functional normal mode.
As is well known, there is often a need to have control over the clock signal that is communicated to the individual scan flops. To achieve this control, it is known to introduce some type of gating logic that is external to the individual scan flops. By introducing external clock gating logic, better control is provided as to when the scan flops change state. When a larger number of scan flops are used in a particular design, there is also a need to perform buffering on the clock lines. The buffering circuitry is generally designed to be well balanced such that all of the scan flops will still clock at about the same time. However, if both clock gating and clock buffering is desired, the clock line will have both clock gating and buffering circuitry.
To accurately test the timing parameters of the circuit design, delays introduced by the clock gating and the clock buffering will have to be accounted for during the delay calculation. This is required so that all of the scan flops will clock at about the same time. Unfortunately, a difficulty can arise in determining whether the clock buffering should be performed before or after the gating logic. In many cases, the introduction of clock buffering logic can complicate timing calculations so much that standard analysis tools find it difficult to accurately test data setup and hold times relative to clock. An exemplary commercially available analysis tool is called Sunrise™, and is available from Synopsys, of Mountain View, Calif.
Known prior art designs that find the need for gated clocks, generally utilize external clock gating circuitry. For instance, U.S. Pat. No. 5,598,112, which is hereby incorporated by reference, describes a circuit for generating a demand-based gated clock. As taught therein, an external circuit
50
is used to generate a gated clock to the register
10
. The external gating circuitry will therefore have to be accounted for during the timing analysis of the IC design. In some cases, when the external gating logic circuitry grows relatively large, typical software analysis tools will fail to accurately generate a testing result. In such cases, designers are often called upon to perform very time consuming manual delay calculations. For very large designs, manual calculations are not only time consuming, but they can be prone to human error. Any degree of introduced error will therefore have the disadvantage of decreasing the reliability of the testing.
In view of the foregoing, there is a need for scan flop circuitry that enables clock gating, but does not introduce additional external logic that can complicate clock buffering or other automated testing operations.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a scan flop circuit that incorporates internal clock gating capabilities. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, or a device. Several inventive embodiments of the present invention are described below.
In one embodiment, a gated clock scan flop circuit is disclosed. The scan flop includes a data terminal D, a scan input terminal SI, a scan enable terminal SE, a clock terminal CLK, a clock gate terminal G, and an output Q and an inverse output /Q. The scan flop also has internally integrated scan flop circuitry that can be accessed by external logic circuitry by way of the terminals D, SI, SE, CLK, G, Q, and /Q. Preferably, the internally integrated scan flop circuitry includes: (i) a first gate that is configured to receive input connections from both the scan input terminal SI and the clock gate terminal G, (ii) a latch circuit that is configured to receive the clock gate terminal G and track its input while the clock terminal CLK is inactive, (iii) a second gate that is configured to receive input connections from both the scan enable terminal SE and the latch circuit; and (iv) a third gate that is configured to receive input connections from both the clock terminal CLK and an output of the second gate.
In another embodiment, a scan flop circuit is disclosed. The scan flop circuit includes: (a) a sub-scan flop circuit that includes a multiplexer and a flip flop circuit; (b) a data terminal D that is connected to the sub-scan flop circuit; (c) a first logic gate that is configured to receive a scan input terminal SI and a clock gate terminal G, and the first logic gate has a first logic gate output that is connected to the sub-scan flop circuit; (d) a scan enable terminal SE that is connected to the sub-scan flip circuit; (e) a latch circuit that is configured to receive the clock gate terminal G; (f) a second logic gate that is configured to receive the scan enable terminal SE and the latch circuit output, the second logic gate having a second logic gate output; (g) a third logic gate that is configured to receive a clock terminal CLK and the second logic gate output, the third logic gate having a third logic gate output that is connected to the sub-scan flop circuit; and (h) an output Q and a complementary output /Q. In this embodiment, the first logic gate, the latch, the second logic gate, the third logic gate, and the sub-scan flop circuit are internal circuit components of the scan flop circuit.
In still a further embodiment, a method of making a scan flop circuit is disclosed. The method includes: (a) building a sub-scan flop circuit, the sub-scan flop circuit has a multiplexer and a flip flop circuit; (b) defining a data terminal D that is connected to the sub-scan flop circuit; (c) defining a first logic gate that is configured to receive a scan input terminal SI and a clock gate terminal G, the first logic gate having a first logic gate output that is connected to the sub-scan flop circuit; (d) defining a scan enable terminal SE that is connected to the sub-scan flip circuit; (e) defining a latch circuit that is configured to receive the clock gate terminal G; (f) defining a second logic gate that is configured to receive the scan enable terminal SE and the latch circuit output, the second logic gate having a second logic gate output; (g) defining a third logic gate that is configured to receive a clock terminal CLK and the second logic gate output, the third logic gate having a third logic gate output that is connected to the sub-scan flop circuit; and (h) defining an output Q and a complementary output /Q.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


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