High performance, low power differential latch

Details High performance, low power differential latch High performance, low power differential latch

2002-11-08

2003-12-02

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S212000, C327S055000

Reexamination Certificate

active

06657471

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to local clock distribution and low power circuit design
1. Trademarks
IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
2. Background
In modern microprocessors, an important new design obstacle has begun to emerge. Now, instead of a designer spending most of his time maximizing the speed of his logic, power consumption must be considered a more critical parameter. Recent studies have shown that the primary problem with power distribution lies in the clock, more specifically, the local clock and latch power, and with feature sizes decreasing and scale of integration increasing, this problem will continue to worsen. Thus, it can be concluded that improvements in clock distribution techniques, especially local clock distribution, and latch design, have the potential to lead to major power savings overall.
SUMMARY OF THE INVENTION
Many prior-art latch designs employ a simple complementary pull down network to write data into the latch. Unfortunately, due to the small transistor sizes, these designs can be, slow compared to the pass gate based latch designs. While it would be possible to improve the performance by increasing transistor size, it is important to consider power when doing so. Since larger transistors mean more power consumption, this solution is unacceptable. Instead, an additional small logic structure can be added to the latch to increase the performance of the typically slow pull-up of the complementary latch with a minimal increase in power consumption. Additional improvements also make it possible to save much of the clock power dissipated in driving these latches.


REFERENCES:
patent: 6344761 (2002-02-01), Nishimura et al.
patent: 6373782 (2002-04-01), Ikeda
patent: 6396309 (2002-05-01), Zhao et al.
patent: 6498516 (2002-12-01), Yau

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