High performance dynamic logic compatible and scannable transpar

Details High performance dynamic logic compatible and scannable transpar High performance dynamic logic compatible and scannable transpar

1996-02-21

1998-06-16

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327212, 327218, H03K 19096

Patent

active

057677174

ABSTRACT:
A high performance dynamic logic compatible transparent latch is provided. The latch comprises a first switchable invertor circuit, a second invertor circuit, and a third switchable invertor circuit. The first invertor, having a data input, a clock input and an output, is enabled by a first phase of an input clock and is disabled by a second phase of the input clock. The second invertor has an input connected to the first invertor output. The third invertor has a clock input, and is enabled by the second phase of the input clock and disabled by the first phase of the input clock, and further has an input connected to the second invertor output and an output connected to the second invertor input.

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Solid State Circuits -"High Speed CMOS Circuits Technique" By Jipen Yuan and Christer Svensson. -Feb., 1989.

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