Add-compare-select arithmetic unit for Viterbi decoder

Add-compare-select processor in Viterbi decoder

Address error detection by merging a polynomial-based CRC...

Address generation for contention-free memory mappings of...

Address information detecting apparatus and address...

Addressing strategy for Viterbi metric computation

Algebraic construction of LDPC (Low Density Parity Check)...

Algebraic decoder and method for correcting an arbitrary...

Algebraic geometric code adapted to error bursts

Algebraic low-density parity check code design for variable...

Algebraic soft decoding of reed-solomon codes

Algorithm for a memory-based Viterbi decoder

Algorithm to test LPAR I/O subsystem's adherence to LPAR I/O...

Allocating data bursts and supporting hybrid auto...

Ameliorating the adverse impact of burst errors on the...

Amplifying magnitude metric of received signals during...

Amplifying magnitude metric of received signals during...

Analog to digital converter with encoder circuit and testing...

Apparatus and method for accommodating loss of signal

Apparatus and method for adaptive hybrid ARQ concatenated FEC