I/O interface cell for use with optional pad
I/O interface for multilevel circuits
I/O transceiver having a pulsed latch receiver circuit
I2C repeater with voltage translation
IC card input/output control circuit
IC chip using a common multiplexor logic element for performing
IC devices with a built-in circuit for protecting internal infor
IC having memoried terminals and zero-delay boundary scan
IC having programmable digital logic cells
IC output signal path with switch, bus holder, and buffer
IC with digital and analog circuits and mixed signal I/O pins
IC with digital and analog circuits and mixed signal I/O pins
IC with dual input output memory buffer
IDDQ testable programmable logic arrays
IIL reset circuit
Impedance adaptation process and device for a transmitter and/or
Impedance adjustable circuit having on-chip adjustable...
Impedance adjusting circuit
Impedance adjusting circuit and impedance adjusting method
Impedance adjusting circuit and semiconductor memory device...