IC having memoried terminals and zero-delay boundary scan

Details IC having memoried terminals and zero-delay boundary scan IC having memoried terminals and zero-delay boundary scan

1997-04-11

1999-03-09

Santamauro, Jon

Electronic digital logic circuitry

With test facilitating feature

371 2232, 326 40, H03K 1900, G01R 3128

Patent

active

058805958

ABSTRACT:
An electronic integrated circuit includes a signal path for carrying a functional signal between functional logic (15) and an external terminal, which signal path includes a memory element (121, 123, 127). When a test signal is applied to the signal path, a switch (S) of the memory element isolates the test signal from the functional signal.

REFERENCES:
patent: 4825439 (1989-04-01), Sakashita et al.
patent: 4860290 (1989-08-01), Daniels et al.
patent: 5134314 (1992-07-01), Wehrmacher
patent: 5175447 (1992-12-01), Kawasaki et al.
patent: 5252917 (1993-10-01), Kadowski
patent: 5488614 (1996-01-01), Shima
patent: 5491699 (1996-02-01), Scheuermann et al.
David George, "Use a Reprogrammable Approach to Boundary Scan for FPGAs", EDN Electrical Design News, vol. 38, No. 16, 5 Aug. 1993, pp. 97-100.
Nai-Chi Lee, "A Hierarchical Analog Test Bus Framework for Testing Mixed-Signal Integrated Circuits and Printed Circuit Boards", Journal of Electronic Testing, vol. 4, No. 4, Nov. 1, 1993, pp. 361-368.
Bulent Dervisoglu, "IEEE P1149.2 Description and Status Report", IEEE, Sep. 1992, pp. 79-81.
L. Whetsel, "IEEE Std. 1149.1--An Introduction", NEPCON, Feb. 1993, 10 pages.
Unapproved Draft IEEE P1149.2-D2.5, "Extended Digital Serial Subset", IEEE, Aug. 1994, pp. 1-37.
Dilip K. Bhavsar, "Chapter 17. Cell Designs that Help Test Interconnect Shorts," IEEE, 1990 pp. 183-189.
W.C. Bruce, Michael G. Gallup, Grady Giles, and Tom Munns, "Implementing 1149.1 on CMOS Microprocessors", IEEE, 1992, International Test Conference 1991, Paper BP-91, pp. 999-1006.

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