Impedance adjusting circuit and impedance adjusting method

Details Impedance adjusting circuit and impedance adjusting method Impedance adjusting circuit and impedance adjusting method

2006-07-25

2009-06-16

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S026000

Reexamination Certificate

active

07548087

ABSTRACT:
An impedance adjusting circuit for adjusting an impedance of an output buffer of a DDR2 memory, using an OCD impedance adjusting function, from a side of a memory controller, includes first and second terminals, first and second switches, a comparator, and a control circuit. The DDR2 memory has an OCD impedance adjusting function and includes a first output buffer and a second buffer each having a pull-up buffer and a pull-down buffer that receive an input signal in common and with impedances thereof capable of being variably set. The first and second terminals receive first and second signals output from the first buffer and the second buffers, respectively. The first and second switches are connected between the first terminal and the second terminal in series. The comparator compares a reference voltage VREF with a voltage at a connection node between the first and second switches. The control circuit receives a comparison result from the comparator to perform control for adjustably setting the impedance of the first buffer and/or the impedance of the second buffer, and also performs on/off control of the first and second switches.

REFERENCES:
patent: 2004/0169525 (2004-09-01), Kerr
patent: 11-177380 (1999-07-01), None
Technical Note, New Functions of DDR2 SDRAM, off-Chip Driver (OCD), Jan. 2005, Document No. J05 94E10 (Ver. 1.0) (http://www.elpida.com).

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