IDDQ testable programmable logic arrays

Details IDDQ testable programmable logic arrays IDDQ testable programmable logic arrays

1998-03-03

2000-10-03

Tokar, Michael

Electronic digital logic circuitry

With test facilitating feature

326 41, 326 46, H03K 1900

Patent

active

061278386

ABSTRACT:
The invention relates to an integrated circuit comprising a dynamic CMOS Programmable Logic Array (PLA) with an AND plane and an OR plane. The invention also relates to a method for testing such a circuit. A PLA according to the invention is provided with means enabling detection of bridging faults. Adjacent lines can be driven to complementary logic levels. Crosspoint transistors can be switched off. In this way, bridging faults between lines give rise to an observable elevated quiescent power supply current (IDDQ).

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patent: 4517672 (1985-05-01), Pfleiderer et al.
patent: 4536881 (1985-08-01), Kasuya
patent: 4768196 (1988-08-01), Jou et al.
patent: 4920515 (1990-04-01), Obata
patent: 5083047 (1992-01-01), Horie et al.
patent: 5504755 (1996-04-01), Nozuyama

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