4. Electronic digital logic circuitry
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Chip level bias for buffers driving voltages greater than transi

Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor
Patent

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Circuit and method for contact pad isolation

Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
Reexamination Certificate

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Circuit and method for differentiating multiple modules

Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
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Circuit for contact pad isolation

Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
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Circuitry for a low internal voltage integrated circuit

Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
Reexamination Certificate

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Circuits and method for body contacted and backgated...

Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor
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Clock driver circuit in a centrally located macro cell layout re

Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
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Contact ring architecture

Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor
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Coupling of signals between adjacent functional blocks in an...

Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor
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